As stated above, the tools generally infer I/O buffers if you don't already have them in your RTL - connecting the top-level ports of the FPGA to the outside world... If you don't put them there, you'll generally still see them in the synthesized (or technology) netlist. Otherwise, nothing would be connected.
There are some cases it can't do that (differential buffers like IBUFDS/OBUFDS for legacy reasons perhaps) and there are some cases where you don't want it to do that, e.g. sub-level module in partial reconfiguration, hierarchical design, out of context as part of a larger separate design, etc. or you want more control of the underlying primitives (as suggested too). But it does it by default since that is what most people and flows would want/need.
Since you are using ISE (and presumably XST), see the -iobuf option more info, e.g. page 318 of https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst_v6s6.pdf
Some flows like out-of-context mode should automatically turn this off. And since XPS (in EDK) synthesizes individual IP cores separately as part of a larger design (versus global synthesis), it turns it off too for those levels of the hierarchy when synthesizing the cores.
Cheers,
bt
