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Muralikumar_M
Observer
Observer
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Registered: ‎05-25-2020

impact of IOBUF

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Hii...

   In xilinx ISE 14.7 , what is the purpose of using IBUF and OBUF.

without using IBUF and OBUF, Pin function is looking same...

can anybody help me to get this...?

 

Murali

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barriet
Xilinx Employee
Xilinx Employee
526 Views
Registered: ‎08-13-2007

As stated above, the tools generally infer I/O buffers if you don't already have them in your RTL - connecting the top-level ports of the FPGA to the outside world... If you don't put them there, you'll generally still see them in the synthesized (or technology) netlist. Otherwise, nothing would be connected.

There are some cases it can't do that (differential buffers like IBUFDS/OBUFDS for legacy reasons perhaps) and there are some cases where you don't want it to do that, e.g. sub-level module in partial reconfiguration, hierarchical design, out of context as part of a larger separate design, etc. or you want more control of the underlying primitives (as suggested too). But it does it by default since that is what most people and flows would want/need.

Since you are using ISE (and presumably XST), see the -iobuf option more info, e.g. page 318 of https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst_v6s6.pdf

Some flows like out-of-context mode should automatically turn this off. And since XPS (in EDK) synthesizes individual IP cores separately as part of a larger design (versus global synthesis), it turns it off too for those levels of the hierarchy when synthesizing the cores.

Cheers,

bt

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calibra
Voyager
Voyager
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Registered: ‎06-20-2012

IBUF/OBUF are special cells to connect the FPGA with the external world.

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Muralikumar_M
Observer
Observer
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Registered: ‎05-25-2020
Thanks for Your Reply,
But This Components are necessary or optional..?
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calibra
Voyager
Voyager
533 Views
Registered: ‎06-20-2012

Absolutely mandatory.

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bruce_karaffa
Scholar
Scholar
532 Views
Registered: ‎06-21-2017

These components are necessary.  If you do not explicitly instantiate them, ISE or Vivado will add them..Explicitly instantiating them allows you to set some generics and attributes in your code.

barriet
Xilinx Employee
Xilinx Employee
527 Views
Registered: ‎08-13-2007

As stated above, the tools generally infer I/O buffers if you don't already have them in your RTL - connecting the top-level ports of the FPGA to the outside world... If you don't put them there, you'll generally still see them in the synthesized (or technology) netlist. Otherwise, nothing would be connected.

There are some cases it can't do that (differential buffers like IBUFDS/OBUFDS for legacy reasons perhaps) and there are some cases where you don't want it to do that, e.g. sub-level module in partial reconfiguration, hierarchical design, out of context as part of a larger separate design, etc. or you want more control of the underlying primitives (as suggested too). But it does it by default since that is what most people and flows would want/need.

Since you are using ISE (and presumably XST), see the -iobuf option more info, e.g. page 318 of https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst_v6s6.pdf

Some flows like out-of-context mode should automatically turn this off. And since XPS (in EDK) synthesizes individual IP cores separately as part of a larger design (versus global synthesis), it turns it off too for those levels of the hierarchy when synthesizing the cores.

Cheers,

bt

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