ip:fifo_gerator:13.2 spartan7 license

[froby66]

Hello

I'm using a xc7s50csga324-1 fpga

with

Vivado v2018.2.2 (64-bit)

SW Build: 2348494 on Mon Oct 1 18:25:44 MDT 2018

IP Build: 2318053 on Mon Oct 1 21:44:26 MDT 2018

and license V_WebPACK

I created my code, generated the bitstream and programmed the configuration Memory device by a Platform Cable USB DLC9G.

I remove and give power keeping the DLC9G attached to my board, so doing the fpga work well, the fifo(generate by IP FIFO Generator 13.2(Rev.2)  behaves as expected

While if I remove and give power without the DLC9G attached to my card,  the fifo in the fpga doesn't work as expected;

then if I attach the DLC9G to my board  "magically" the fifo resumes work as expected and continues to work properly even if then detach the DLC9G.

This is true if and only if the VIVADO SW is active

nb: when the fifo works badly, it resets its content to zero every 242.24ms

Therefore my doubt is that the SW VIVADO through the DLC9G transmits to the fpga some code that allows it to work properly

Is there any problem of lincense?

Best regards

Roberto

[harshit]

Can you try to re-generate the core? if that helps. Please do share the design properties using the below command:
report_property -all [current_design]
Make sure to open the implemented design.

Thanks
Harshit

[froby66]

Hi

Rebuilding the core doesn't change the problem

I can not generate the report because Tcl console

gives me these:

report_property -all [current_design]

WARNING: [Vivado 12-628] No current design set.

ERROR: [Common 17-58] '' is not a valid first class Tcl object.

[harshit]

You need to open the implemented design and run the above command.

Thanks
Harshit

[froby66]

sorry

but TlcConsole gives me an error

[froby66]

  report_property -all [current_design]  fails  ,

while the others report_property  works

   report_property -all [current_project] 

    report_property -all [current_fileset]  

    report_property -all [current_run]

  I don't know why

report_property -all [current_design]
WARNING: [Vivado 12-628] No current design set.
ERROR: [Common 17-58] '' is not a valid first class Tcl object.

report_property -all [current_fileset]
Property                      Type     Read-only  Value
CLASS                         string   true       fileset
DESIGN_MODE                   enum     false      RTL
EDIF_EXTRA_SEARCH_PATHS       string*  false     
ELAB_LINK_DCPS                bool     false      1
ELAB_LOAD_TIMING_CONSTRAINTS  bool     false      1
FILESET_TYPE                  string   true       DesignSrcs
GENERIC                       string*  false     
INCLUDE_DIRS                  string*  false     
LIB_MAP_FILE                  string   false     
LOOP_COUNT                    int      false      1000
NAME                          string   false      sources_1
NEEDS_REFRESH                 bool     true       0
TOP                           string   false      FPGA_HeadControl_KMi_Main_VHDL
VERILOG_DEFINE                string*  false     
VERILOG_UPPERCASE             bool     false      0
report_property -all [current_project]
Property                                 Type     Read-only  Value
BASE_BOARD_PART                          string   true      
BOARD_CONNECTIONS                        string*  false     
BOARD_PART                               string   false     
CLASS                                    string   true       project
COMPXLIB.ACTIVEHDL_COMPILED_LIBRARY_DIR  string   false      D:/LAVORI/FPGA/VIVADO_2018_2_HEAD_CONTROL_KMi_v28_00_01/VIVADO_2018_2_HEAD_CONTROL_KMi_v28_00_01.cache/compile_simlib/activehdl
COMPXLIB.FUNCSIM                         bool     false      1
COMPXLIB.IES_COMPILED_LIBRARY_DIR        string   false      D:/LAVORI/FPGA/VIVADO_2018_2_HEAD_CONTROL_KMi_v28_00_01/VIVADO_2018_2_HEAD_CONTROL_KMi_v28_00_01.cache/compile_simlib/ies
COMPXLIB.MODELSIM_COMPILED_LIBRARY_DIR   string   false      D:/LAVORI/FPGA/VIVADO_2018_2_HEAD_CONTROL_KMi_v28_00_01/VIVADO_2018_2_HEAD_CONTROL_KMi_v28_00_01.cache/compile_simlib/modelsim
COMPXLIB.OVERWRITE_LIBS                  bool     false      0
COMPXLIB.QUESTA_COMPILED_LIBRARY_DIR     string   false      D:/LAVORI/FPGA/VIVADO_2018_2_HEAD_CONTROL_KMi_v28_00_01/VIVADO_2018_2_HEAD_CONTROL_KMi_v28_00_01.cache/compile_simlib/questa
COMPXLIB.RIVIERA_COMPILED_LIBRARY_DIR    string   false      D:/LAVORI/FPGA/VIVADO_2018_2_HEAD_CONTROL_KMi_v28_00_01/VIVADO_2018_2_HEAD_CONTROL_KMi_v28_00_01.cache/compile_simlib/riviera
COMPXLIB.TIMESIM                         bool     false      1
COMPXLIB.VCS_COMPILED_LIBRARY_DIR        string   false      D:/LAVORI/FPGA/VIVADO_2018_2_HEAD_CONTROL_KMi_v28_00_01/VIVADO_2018_2_HEAD_CONTROL_KMi_v28_00_01.cache/compile_simlib/vcs
COMPXLIB.XSIM_COMPILED_LIBRARY_DIR       string   false     
CORECONTAINER.ENABLE                     bool     false      1
DEFAULT_LIB                              string   false      xil_defaultlib
DIRECTORY                                string   true       D:/LAVORI/FPGA/VIVADO_2018_2_HEAD_CONTROL_KMi_v28_00_01
DSA.ROM.DEBUG_TYPE                       int      false      0
DSA.ROM.PROM_TYPE                        int      false      0
ENABLE_OPTIONAL_RUNS_STA                 bool     false      0
EXAMPLE_PROJECT                          bool     true       0
GENERATE_IP_UPGRADE_LOG                  bool     false      1
ID                                       string   true       eec9e86eadcf4186b646fea56b9d4c91
IP_CACHE_PERMISSIONS                     string*  false      read write
IP_INTERFACE_INFERENCE_PRIORITY          string*  false     
IP_OUTPUT_REPO                           string   false      D:/LAVORI/FPGA/VIVADO_2018_2_HEAD_CONTROL_KMi_v28_00_01/VIVADO_2018_2_HEAD_CONTROL_KMi_v28_00_01.cache/ip
IP_REPO_PATHS                            string*  false     
IS_READONLY                              bool     false      0
NAME                                     string   true       VIVADO_2018_2_HEAD_CONTROL_KMi_v28_00_01
PART                                     part     false      xc7s50csga324-1
PROJECT_TYPE                             enum     false      Default
PR_FLOW                                  bool     false      0
SIM.IP.AUTO_EXPORT_SCRIPTS               bool     false      1
SIM.USE_IP_COMPILED_LIBS                 bool     false      1
SIMULATOR_LANGUAGE                       enum     false      Mixed
SOURCE_MGMT_MODE                         enum     false      DisplayOnly
TARGET_LANGUAGE                          enum     false      VHDL
TARGET_SIMULATOR                         string   false      XSim
XPM_LIBRARIES                            string*  false      XPM_CDC XPM_MEMORY
XSIM.ARRAY_DISPLAY_LIMIT                 string   false      1024
XSIM.RADIX                               enum     false      hex
XSIM.TIME_UNIT                           enum     false      ns
XSIM.TRACE_LIMIT                         string   false      65536

[harshit]

As I said you need to open the implemented design.

Without opening the implemented design: Error which you have.

Open the implemented design. You won't hit the error and get the correct results.

[froby66]

Hi

thanks for your explanations

here is finally the requested report

report_property -all [current_design]
Property                                  Type     Read-only  Value
BITSTREAM.CONFIG.CCLKPIN                  enum     false     
BITSTREAM.CONFIG.CCLK_TRISTATE            enum     false     
BITSTREAM.CONFIG.CONFIGFALLBACK           enum     false     
BITSTREAM.CONFIG.CONFIGRATE               enum     false      66
BITSTREAM.CONFIG.DCIUPDATEMODE            enum     false     
BITSTREAM.CONFIG.DONEPIN                  enum     false     
BITSTREAM.CONFIG.EXTMASTERCCLK_EN         enum     false     
BITSTREAM.CONFIG.INITPIN                  enum     false     
BITSTREAM.CONFIG.INITSIGNALSERROR         enum     false     
BITSTREAM.CONFIG.M0PIN                    enum     false      PULLNONE
BITSTREAM.CONFIG.M1PIN                    enum     false      PULLNONE
BITSTREAM.CONFIG.M2PIN                    enum     false      PULLNONE
BITSTREAM.CONFIG.NEXT_CONFIG_ADDR         hex      false     
BITSTREAM.CONFIG.NEXT_CONFIG_REBOOT       enum     false     
BITSTREAM.CONFIG.OVERTEMPPOWERDOWN        enum     false     
BITSTREAM.CONFIG.PERSIST                  enum     false      YES
BITSTREAM.CONFIG.PROGPIN                  enum     false     
BITSTREAM.CONFIG.REVISIONSELECT           enum     false     
BITSTREAM.CONFIG.REVISIONSELECT_TRISTATE  enum     false     
BITSTREAM.CONFIG.SELECTMAPABORT           enum     false     
BITSTREAM.CONFIG.SPI_32BIT_ADDR           enum     false      YES
BITSTREAM.CONFIG.SPI_BUSWIDTH             enum     false      4
BITSTREAM.CONFIG.SPI_FALL_EDGE            enum     false     
BITSTREAM.CONFIG.TCKPIN                   enum     false     
BITSTREAM.CONFIG.TDIPIN                   enum     false     
BITSTREAM.CONFIG.TDOPIN                   enum     false     
BITSTREAM.CONFIG.TIMER_CFG                hex      false     
BITSTREAM.CONFIG.TIMER_USR                hex      false     
BITSTREAM.CONFIG.TMSPIN                   enum     false     
BITSTREAM.CONFIG.UNUSEDPIN                enum     false     
BITSTREAM.CONFIG.USERID                   hex      false     
BITSTREAM.CONFIG.USR_ACCESS               string   false     
BITSTREAM.ENCRYPTION.ENCRYPT              enum     false      NO
BITSTREAM.ENCRYPTION.ENCRYPTKEYSELECT     enum     false     
BITSTREAM.ENCRYPTION.HKEY                 hex      false     
BITSTREAM.ENCRYPTION.KEY0                 hex      false     
BITSTREAM.ENCRYPTION.KEYFILE              file     false     
BITSTREAM.ENCRYPTION.STARTCBC             hex      false     
BITSTREAM.GENERAL.COMPRESS                enum     false      TRUE
BITSTREAM.GENERAL.CRC                     enum     false     
BITSTREAM.GENERAL.DEBUGBITSTREAM          enum     false     
BITSTREAM.GENERAL.DISABLE_JTAG            enum     false     
BITSTREAM.GENERAL.JTAG_XADC               enum     false     
BITSTREAM.GENERAL.PERFRAMECRC             enum     false     
BITSTREAM.GENERAL.XADCENHANCEDLINEARITY   enum     false     
BITSTREAM.GENERAL.XADCPOWERDOWN           enum     false     
BITSTREAM.READBACK.ACTIVERECONFIG         enum     false     
BITSTREAM.READBACK.ICAP_SELECT            enum     false     
BITSTREAM.READBACK.SECURITY               enum     false     
BITSTREAM.READBACK.XADCPARTIALRECONFIG    enum     false     
BITSTREAM.STARTUP.DONEPIPE                enum     false     
BITSTREAM.STARTUP.DONE_CYCLE              enum     false     
BITSTREAM.STARTUP.GTS_CYCLE               enum     false     
BITSTREAM.STARTUP.GWE_CYCLE               enum     false     
BITSTREAM.STARTUP.LCK_CYCLE               enum     false     
BITSTREAM.STARTUP.MATCH_CYCLE             enum     false     
BITSTREAM.STARTUP.STARTUPCLK              enum     false     
BMM_FILE                                  string   false     
CFGBVS                                    enum     false      VCCO
CLASS                                     string   true       design
CONFIG_MODE                               enum     false      SPIx4
CONFIG_VOLTAGE                            enum     false      3.3
CONSTRSET                                 fileset  true       constrs_4
DCP_VERSION                               string   true       Vivado v2018.2.2 (64-bit) SW Build 2348494 on Mon Oct  1 18:25:44 MDT 2018
DEFAULT_IOSTANDARD                        string   false     
HD.ISOLATED                               bool     false     
HD.OVERRIDE_PERSIST                       bool     false     
HD.PARTITION                              bool     false     
HD.RECONFIGURABLE                         bool     false     
HD.TANDEM_BITSTREAMS                      enum     false     
IS_BLOCK                                  bool     true       0
IS_PRSHELL_DESIGN                         bool     true      
KEEP_COMPATIBLE                           string*  false     
KEEP_HIERARCHY                            enum     false     
MLO_VERSION_NUMBER                        string   false      2018.2.2_9
NAME                                      string   true       impl_CSGA324_1
NEEDS_REFRESH                             bool     true       0
NEEDS_SAVE                                bool     true       0
PART                                      part     true       xc7s50csga324-1
POST_CRC                                  enum     false     
POST_CRC_ACTION                           enum     false     
POST_CRC_FREQ                             int*     false     
POST_CRC_INIT_FLAG                        enum     false     
POST_CRC_SOURCE                           enum     false     
SPEED_LABEL                               string   true      
SPEED_LEVEL_ID                            string   true      
SPEED_LEVEL_ID_DATE                       string   true      
SRCSET                                    fileset  true       sources_1
SUSPEND_FILTER                            string   false     
TOP                                       string   true       FPGA_HeadControl_KMi_Main_VHDL
XLNX_PROJ_DIR                             string   false      D:/LAVORI/FPGA/VIVADO_2018_2_HEAD_CONTROL_KMi_v28_00_01

[harshit · Accepted solution]

Hi,

Thanks for sharing the properties. Most probably PERSIST is creating trouble here. Please remove this property and rerun the implementation and share the results. 

Since you are using SPIx4 mode then PERSIST is not required. Here is the snapshot from UG#470.

Thanks

Harshit

[froby66]

Hi

Many thanks

your solution solved the problem

Best regards

Roberto