09-29-2018 07:07 AM - edited 09-29-2018 07:07 AM
I have a design for the Kintex 7 in the FFG676 package and i debug my fpga is ok with jtag interface.
And i downloads to spi x4 flash,then reset fpga,and fpga can not load bit successfully.
i check UG490,when power up,fpga will transfer opcode(8-bit read command) on data line of spi interface.
i check timing of spi interface,all of them is ok but d[4:0] have nothing,no read command appears on the data lines.
09-29-2018 09:08 AM - edited 09-30-2018 05:54 AM
@dnfestivi "my fpga is ok with jtag interface. And i downloads to spi x4 flash,then reset fpga,and fpga can not load bit successfully. "
Some things to check:
- make sure you have the mode pins correctly set for master SPI configuration
- disconnect the JTAG cable before SPI boot ( a running instance of the JTAG hw_server can disrupt a SPI configuration )
The following document on 7-Series SPI configuration might also be useful:
 AR# 66954 2016.1 and newer Vivado Hardware Manager - Intermittent configuration failures can occur when the FPGA is power cycled and the programming cable is connected.
09-29-2018 06:59 PM
I think the doc you read is UG470.
There're some suggestions for you to debug this issue.
1. what do you mean by "reset fpga"? Can you try to power cycle the FPGA?
2. As brimdavis said, make sure the boot mode is SPI mode.
3. If after power cycle, it still cannot boot. Can you try to reload the bin/mcs file into Flash via Vivado, and make enable blank check, verify and checksum verify options. To check if bin/mcs loading into Flash successfully.
4. If step3 passed, pls read back the configuration register value after boot failed and post it out.