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Participant
Participant
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Registered: ‎09-24-2019

name of state in state machine

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Hello, I have a question of nominating the states in a fsm in vhdl.Is there any benefit to name the states as " 000,001,010,100..." compare to "a,b,c,d..."?

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Scholar
Scholar
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Registered: ‎08-01-2012

Usually in VHDL you use an enumerated type for state machines

type stat_t is (idle, s_do_something, s_do_something_else);

In VHDL this has no inherent bitwise value. But Vivado then gets to chose the encoding based on synthesis settings.

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Explorer
Explorer
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Registered: ‎01-27-2008

@ame,

That's pretty vague as a question but I'll try and help.

Here's what I do in systemverilog:

typedef enum logic [2:0] {IDLE,  START, RUN, MOVE, DONE } cap_state_t;

Then you can use IDLE, START etc were you would use 3'b0, 3'b1.... etc.

Much better to use enumerated types - as you know, inherently what the state is.

Your code becomes simpler and readable. Maintenance / changes are easier.

Jerry

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Participant
Participant
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Registered: ‎09-24-2019

thank you for your response.If I understand well, you give each state name(such as "IDLE") a vector (as "000") to make sure a stable change between each state.But in VHDL, I find that when define a group of state names, they don't give value, just as different names, so I propose this question: whether use string names (one, two, three,four)or directly with array of number like "one hot"(000,001,010,100)

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Scholar
Scholar
259 Views
Registered: ‎08-01-2012

Usually in VHDL you use an enumerated type for state machines

type stat_t is (idle, s_do_something, s_do_something_else);

In VHDL this has no inherent bitwise value. But Vivado then gets to chose the encoding based on synthesis settings.

View solution in original post

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Participant
Participant
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Registered: ‎09-24-2019

Thank you, I understand

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