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Participant
Participant
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Registered: ‎09-24-2019

order of wait on

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Hello, I have wroten a code to test fonction fo plusieur "wait on" and I get a result really weird.Can you please expliant to me how these commands work?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity convolution is
port(
o : out std_logic;
x : out std_logic
);
end entity;

architecture rtl of convolution is
signal a:std_logic;
signal b:std_logic;
begin
a<='0', '1' after 100 ns;
b<='0', '1' after 50 ns, '0' after 100 ns;
process
begin
o<=a;
wait on a;
x<=b;
wait on b;
end process;
end architecture;

result like that:

Screenshot 2020-09-27 173855.png

Why o wasn't initialised like x, and why o changes the state when b changes?

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Scholar
Scholar
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Registered: ‎08-01-2012

wait on N will wait until the signal N has a 'event (ie. it changes). Also remember that processes start at time 0 until they hit a wait statement when there is no sensitivity list

1. At time 0, O <= a; is assigned the initial value of a ('U')/

2. The process waits until a changes, which occurs at time 0 + 1 delta because a changes from 'U' to '0'

3.x <= b, which is now '0' in delta 1

4. process waits until B changes at time 50 ns;

5. o <= a; which is is '0' at 50 ns

6. process waits until a changes at 100 ns

7. x <= b; which at 100ns is '0'

 

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Scholar
Scholar
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Registered: ‎08-01-2012

wait on N will wait until the signal N has a 'event (ie. it changes). Also remember that processes start at time 0 until they hit a wait statement when there is no sensitivity list

1. At time 0, O <= a; is assigned the initial value of a ('U')/

2. The process waits until a changes, which occurs at time 0 + 1 delta because a changes from 'U' to '0'

3.x <= b, which is now '0' in delta 1

4. process waits until B changes at time 50 ns;

5. o <= a; which is is '0' at 50 ns

6. process waits until a changes at 100 ns

7. x <= b; which at 100ns is '0'

 

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Participant
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Registered: ‎09-24-2019

I don't understand for the 3rd 4th point, does b change two times? And in this architecture,b change causes o<=a and  x<=b but a change causes only o<=a?

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Adventurer
Adventurer
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Registered: ‎05-19-2014

@ame wrote:

I don't understand for the 3rd 4th point, does b change two times?


So it is! Make sure to always keep in mind these delta cycles. Signal assignments that are not specified with a real actual positive delay in an after clause will still only take effect later, a delta cycle later. As b is not explicitly initialized, it will start out as 'U'. The first assignment made below will thus become effective at time 0 ns + 1 delta, the second one at time 50 ns. Evaluations of b and, in fact, also of a at time 0 ns (flat) will see uninitialized signals. This is what you witness getting copied into o.

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Participant
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Registered: ‎09-24-2019

Nice.But I wonder when x take the value b=0, won't the code turn to the begining of the process and look if a change another time to execute o<=a? 

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Scholar
Scholar
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Registered: ‎08-01-2012

you've told the process only to wait on b . So any changes in A will be ignored until b changes. If you want it to wait on a or b, and assign both, I suggest the following process:

 

process(a,b)
begin
  o <= a;
  x <= b;
end process;

Using only wait on statement, this process is identical to this:

process
begin
  wait on a,b;
  o <= a;
  x <= b;
end process;

 

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Participant
Participant
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Registered: ‎09-24-2019

Could we say that x change cause to b, but a change cause a and b because "wait on b" is in the end of process, so when 50 ns, b change cause o change, and then a change in 100 ns so o change another time?

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Scholar
Scholar
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Registered: ‎08-01-2012

I dont understand the question.

A process, when simulated, is executed sequentially like any other programming language. So in your original code, when you say "wait on b" , the process is stalled and waiting for b to change, regardless of what any other signals are doing and hence any changes on a are ignored. The same when you write "wait on a", the process stalls until there is a change in a. The signal assignments are scheduled in the same delta cycle. X and O have no effect on the process in the code posted.

The waveform is correct and as described as per my post.

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Participant
Participant
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Registered: ‎09-24-2019

That means that a will influence only the command "o<=a" and b only "x<=b"?

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Scholar
Scholar
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Registered: ‎08-01-2012

What do you mean by "influence".

Because the assignment to O comes after you wait for B, then the "o <= A" assignment only occurs when B changes, and the "x <= b" assignment only occurs when A changes, because you told the process to wait on them. But while it is waiting for A, then all changes in B are ignored, and vice versa.

What is the aim of this code? this form of process is a little more unusual. It is also only acceptable for simulation and cannot be compiled for an FPGA.

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Participant
Participant
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Registered: ‎09-24-2019

I just learn about "wait " command, so I use a code to see what's going on with plusieur "wait on", as you say that it doesn't make sence. influence means the causion, I want to know whether two part assignement divide by two "wait on" are indipendent because in 50 ns, change of b lets o<=a, which means b influnece o but in the code only a should influence o. 

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