cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
104 Views
Registered: ‎09-12-2018

power Xilinx Ultrascale+ FPGA

Hi,

I would like to ask what can be the maximum time delay (if any) to power up different power lines without causing any damage to the FPGA during power sequencing. For example, can you power up VCCINT line only for a few seconds or more and then VCCBRAM for a few seconds before you power up VCCAUX...

Thanks,

Sotiris

 

 

 

 

0 Kudos
2 Replies
Highlighted
Xilinx Employee
Xilinx Employee
78 Views
Registered: ‎08-10-2008

Xilinx does not have this kind of spec. Since there is a POR mointor circuit inside, which means, if you do not power all necessary power rails up, FPGA will be kept in a reset status, I don't think there would be issues if you have short delays between each power rail.

------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------------------
0 Kudos
Highlighted
49 Views
Registered: ‎09-12-2018

Thanks for your fast response. Can you please define "short delays"? For example if for testing purposes there are long delays between the power up of different power rails would it be harmful  for the FPGA?

0 Kudos