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135 Views
Registered: ‎09-11-2019

"Pprogram_B"diiscription

Program_B Discription differ ug380(spartan6) /uf470(artix7)

ug380(spartan6)

When asserted Low for 500 ns
or longer, forces the FPGA to restart its
configuration process by clearing
configuration memory and resetting the
DONE and INIT_B pins after PROGRAM_B
returns High.

My understanding about artix7.

artix7'sTprogram 250ns

When asserted Low for 250 ns
or longer, forces the FPGA to restart its
configuration process by clearing
configuration memory and resetting the
DONE and INIT_B pins after PROGRAM_B
returns High.

Is my understanding correct? 

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Xilinx Employee
Xilinx Employee
99 Views
Registered: ‎08-10-2008

回复: "Pprogram_B"diiscription

So you care about the min pulse width of PROGRAM_B? It's VERY natural that different device families have different requirements; the basic function of PROGRAM_B would always be the same.

Check Tprogram parameter in corresponding datasheet (ds181,ds162, etc) for the min spec of PROGRAM_B.

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