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Visitor target13
Visitor
9,054 Views
Registered: ‎10-21-2007

readback and configuration model

If I configurate the Virtex-II FPGA in Slave Serial model
Can I readback the configuration bits during normal operation?
 
Thank you!
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5 Replies
Xilinx Employee
Xilinx Employee
9,040 Views
Registered: ‎08-14-2007

Re: readback and configuration model

target13,
 
There are two methods of readback in the Virtex-II.  One is through SelectMAP and the other is through JTAG.  If your initial configuration is slave serial, then you are limited to only JTAG readback.  So the answer to your question is yes. 
 
I would recommend that you read the configuration chapter within the Virtex-II UG for more information:
 
Additionally, XAPP138 and XAPP139 go into great detail on both methods.
 
-David
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Visitor target13
Visitor
9,018 Views
Registered: ‎10-21-2007

Re: readback and configuration model

David
            Thank you very much!
and I have an another question: After configurating, Can I change the M2:M0 setting?
If I changed the M2:M0 after configurating, It doesn't work or brings some problem?
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Xilinx Employee
Xilinx Employee
9,008 Views
Registered: ‎08-14-2007

Re: readback and configuration model

target13,
 
The mode pins are dedicated configuration pins and are only sampled after 'house cleaning' is completed (i.e. after PROG is pulsed and INIT_B goes high).  If you want to dynamically change the mode pins via some external glue logic you can although this is not a typical usage of the pins.  If you change the mode pins after initial configuration, your device will not function differently nor will the latest configuration modes be present.  This will only happen after the next configuration.
 
I do not understand why you would want to change the mode pins after the device has been configured.  Can you go into more detail on why you want to do this.
 
-David
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Visitor xyzd040520
Visitor
3,561 Views
Registered: ‎06-15-2011

Re: readback and configuration model

hi,i'm using ML509 FPGA BOARD recently,when i using readback through JTAG, there is a problem. the readback data are all 0s. i followed the method raised in UG191.pdf at page 143 using JTAG to read the configuration memory. i exactly follow the flow, so why can't i read back the data? thank's for you help,expecting your reply.  

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333 Views
Registered: ‎02-18-2019

Re: readback and configuration model

Can you please share some documents , which helps me in READBACK the configured IP, using ICAP on Ultrascale+  FPGA.

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