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Voyager
Voyager
914 Views
Registered: ‎10-12-2016

select startup clock in the edit device properties menu ?

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Hi Friends,

 

while doing some setting in the edit device properties, i come across one option like "select startup clock".

 

vivado gui (after opening synt/imp db)=> Tools => Edit Device properties => statup => select startup clock .

 

1) what is this for  and what will happen if you choose respective provided options(JTAG clk , user clk , etc ) .

 

NOTE:  Any help or suggestion are highly appreciated.

 

Thank You
S Sampath

 

 

-Sampath
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Xilinx Employee
Xilinx Employee
173 Views
Registered: ‎11-12-2019

Hi @ssampath,

I don't know if it help you or not , now , but accidentally I came across your query and thought that below respond might answer it :

  •  FPGA Start-Up Clock
    Specifies the signal that will be used to clock the startup sequence at the end of the FPGA configuration process. Select a clock option in the drop-down list.
    •  CCLK
      Synchronizes the startup sequence to the FPGA Configuration Clock (CCLK). CCLK is internally generated if the FPGA is set for a Master configuration mode; CCLK is an input if the FPGA is set for a Slave configuration mode. This option should be set unless the device will be configured through Boundary Scan (JTAG). Note that when generating a configuration file that will be stored on a configuration PROM, the Start-Up clock should be set for CCLK (even though the PROM itself may be programmed through JTAG).
    •  User Clock
      Synchronizes the startup sequence to a user-defined signal connected to the CLK pin of the STARTUP primitive, which must be instantiated in the user design. Select this option when providing a startup clock to the FPGA other than CCLK or the JTAG clock (this setup is rarely used).
    •  JTAG Clock
      Synchronizes to the JTAG Test Clock (TCK). This clock sequences the TAP controller which provides the control logic for JTAG. Select this option when configuring the FPGA using JTAG. Note that an FPGA that is configured from a PROM should not use this option, use CCLK instead.
    By default, this property is set to CCLK.

    Best Regards,
    Kuldeep

 

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Teacher
Teacher
896 Views
Registered: ‎07-09-2009

good question, 

 

bottom line

 

the fpga needs a clock to start up . Either to read it supplies it to read the bit file itself, or provided to it as the bit file is streamed in.

 

if in doubt, and things work, don't change ...

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008
It depends on the Configuration interface you are using:
JTAG configuration -> TCK the JTAG clk,
Master mode -> CCLK
...
Thanks,
Ivy
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Teacher
Teacher
860 Views
Registered: ‎07-09-2009

 

JTAG is always available, 

  no matter where you boot from,

 

So if you were worried, setting to master mode does not loose you JTAG 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Xilinx Employee
Xilinx Employee
174 Views
Registered: ‎11-12-2019

Hi @ssampath,

I don't know if it help you or not , now , but accidentally I came across your query and thought that below respond might answer it :

  •  FPGA Start-Up Clock
    Specifies the signal that will be used to clock the startup sequence at the end of the FPGA configuration process. Select a clock option in the drop-down list.
    •  CCLK
      Synchronizes the startup sequence to the FPGA Configuration Clock (CCLK). CCLK is internally generated if the FPGA is set for a Master configuration mode; CCLK is an input if the FPGA is set for a Slave configuration mode. This option should be set unless the device will be configured through Boundary Scan (JTAG). Note that when generating a configuration file that will be stored on a configuration PROM, the Start-Up clock should be set for CCLK (even though the PROM itself may be programmed through JTAG).
    •  User Clock
      Synchronizes the startup sequence to a user-defined signal connected to the CLK pin of the STARTUP primitive, which must be instantiated in the user design. Select this option when providing a startup clock to the FPGA other than CCLK or the JTAG clock (this setup is rarely used).
    •  JTAG Clock
      Synchronizes to the JTAG Test Clock (TCK). This clock sequences the TAP controller which provides the control logic for JTAG. Select this option when configuring the FPGA using JTAG. Note that an FPGA that is configured from a PROM should not use this option, use CCLK instead.
    By default, this property is set to CCLK.

    Best Regards,
    Kuldeep

 

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Voyager
Voyager
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Registered: ‎10-12-2016
Pls point me the reference UG if any ?
-Sampath
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