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Explorer
Explorer
10,067 Views
Registered: ‎02-04-2013

spartan-6 ICAP configuration

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Hello everybody,

I was reading about the ICAP fpga configuration, and i could not find any info about the configuration frame length that has to be written to ICAP at once. Is there a specified frame length (similar to page write) that has to be written to icap or does every 16bit data contains all the needed informations for single write?

I would also like to verify the bit stream was written correctly. How can i do that? I assume i need to define some kind of address when reading from ICAP, but i am not sure what part of 16 bit data i wrote to icap contains the information about the address.

Regards
Klemen

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1 Solution

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Xilinx Employee
Xilinx Employee
17,168 Views
Registered: ‎07-31-2012

Re: spartan-6 ICAP configuration

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Hi, 

 

The ICAP lengiht in Spartan 6 is 16 bit width. The ICAP interface is very similar to the SelectMap interface. Try to generate an mcs file with the Select Map option using promgen and that should give you an idea on the frame length which you would need.

 

On the way to verify the bitstream was written correctly, you can read back the configuration data using the readback options from the FPGA. You can readbackk using Selectmap or ICAP or JTAG interfaces. Check Pg 111 onwards of - http://www.xilinx.com/support/documentation/user_guides/ug380.pdf for more information.

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

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7 Replies
Xilinx Employee
Xilinx Employee
17,169 Views
Registered: ‎07-31-2012

Re: spartan-6 ICAP configuration

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Hi, 

 

The ICAP lengiht in Spartan 6 is 16 bit width. The ICAP interface is very similar to the SelectMap interface. Try to generate an mcs file with the Select Map option using promgen and that should give you an idea on the frame length which you would need.

 

On the way to verify the bitstream was written correctly, you can read back the configuration data using the readback options from the FPGA. You can readbackk using Selectmap or ICAP or JTAG interfaces. Check Pg 111 onwards of - http://www.xilinx.com/support/documentation/user_guides/ug380.pdf for more information.

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

View solution in original post

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Community Manager
Community Manager
10,043 Views
Registered: ‎07-23-2012

Re: spartan-6 ICAP configuration

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I would also like to verify the bit stream was written correctly. How can i do that? 


After configuration, a CRC check is performed if the switch "-g CRC" is enabled in the bitgen settings. This will make sure that the written configuration data is not corrupt.

 


I assume i need to define some kind of address when reading from ICAP, but i am not sure what part of 16 bit data i wrote to icap contains the information about the address.


ICAP is used to read/write data to configuration registers. 

Please take a look at the highlighted content in the below snippet.

 

In the first highlighted ICAP command, we are telling the ICAP primitive that we are going to perform write operation to CMD register.

 

The second command states the value that we are going to write into CMD.

 

For more details on type-1 or type-2 packets and the addresses of config registers, refer to "Packet Types" section of http://www.xilinx.com/support/documentation/user_guides/ug380.pdf

 

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9,987 Views
Registered: ‎02-22-2014

Re: spartan-6 ICAP configuration

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#include "xparameters.h" /* XPAR parameters */
#include "xhwicap.h" /* HWICAP device driver */
#include "xintc.h"
#include "xil_exception.h" /* Exceptions */
#include <stdio.h>

void print(char *);

#define HWICAP_DEVICE_ID XPAR_HWICAP_0_DEVICE_ID
#define HWICAP_IRPT_INTR XPAR_INTC_0_HWICAP_0_VEC_ID
#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID

int HwIcapTestAppExample(u16 DeviceId);
static int HwIcapSetupInterruptSystem(XIntc* IntcInstancePtr, XHwIcap *HwIcapPtr,u16 IntrId );
void HwIcapIntrHandler(void *CallBackRef, u32 StatusEvent, u32 WordCount);

static XHwIcap HwIcap; /* The instance of the HWICAP device */
static XIntc IntcInstance;

volatile int TransferInProgress;
int Error;
void print(char *str);




int main(void)
{
int Status;

/*
* Run the HwIcap Example, specify the Device ID generated in
* xparameters.h
*/
Status = HwIcapTestAppExample(HWICAP_DEVICE_ID);
if (Status != XST_SUCCESS) {
print("Failure");
}
else {
print("Success");
}
}
int HwIcapTestAppExample(u16 HwIcapDeviceId)
{
int Status;

XHwIcap_Config *ConfigPtr;
//u32 ConfigRegData32[8]={0xfffffff, 0xAA995566, 0x3261a9c9, 0x32810316, 0x32a10000, 0x32c10300, 0x30a1000e, 0x20002000};

u16 ConfigRegData16[14]={0xffff, 0xAA99, 0x5566, 0x3261, 0xA9c9, 0x3281, 0xc0316, 0x32a1, 0x0000, 0x32c1, 0x0300, 0x30a1, 0x000e, 0x2000};
//u32 ConfigRegData16[8]={0xfffffff, 0xAA995566, 0x32619593, 0x3281D068, 0x32a10000, 0x32c10B00, 0x30a1000e, 0x20002000};

//u32 ConfigRegData16[14]={XHI_DUMMY_PACKET, XHI_SYNC_PACKET1, XHI_SYNC_PACKET2, XHwIcap_Type1Write(XHI_GENERAL1),
//0x9593, XHwIcap_Type1Write(XHI_GENERAL2), 0Xc068, XHwIcap_Type1Write(XHI_GENERAL3), 0X0000,
//XHwIcap_Type1Write(XHI_GENERAL4),0Xc000, XHwIcap_Type1Write(XHI_CMD), XHI_CMD_IPROG, XHI_NOOP_PACKET};
/*
* Initialize the HwIcap driver.
*/
ConfigPtr = XHwIcap_LookupConfig(HwIcapDeviceId);
if (ConfigPtr == NULL) {
return XST_FAILURE;
}
print("Successfully initialized");
Status = XHwIcap_CfgInitialize(&HwIcap, ConfigPtr,ConfigPtr->BaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
print("\n configured");

/*
* Perform a self-test to ensure that the hardware was built correctly.
*/
Status = XHwIcap_SelfTest(&HwIcap);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}

print("\n self test passed");
/*
* Read the ID Code register inside the FPGA.

u32 reg;
Status = XHwIcap_GetConfigReg(&HwIcap, XHI_IDCODE, &reg);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
*/
//u32 from_sample16[28]={0xFFFF,0xFFFF,0xAA99,0x5566,0x31E1,0xFFFF,0x3261,0xA9C9,0x3281,0x0316,0x32A1,0x0000,0x32C1,0x0300,0x32E1,0x0000,0x30A1,0x0000,0x3301,0x2100,0x3201,0x001F,0x30A1,0x000E,0x2000,0x2000,0x2000,0x2000};
//u32 from_sample32[14]={0xFFFFFFFF,0xAA995566,0x31E1FFFF,0x3261A9C9,0x32810316,0x32A10000,0x32C10300,0x32E10000,0x30A10000,0x33012100,0x3201001F,0x30A1000E,0x20002000,0x20002000};
Status = HwIcapSetupInterruptSystem(&IntcInstance,&HwIcap,HWICAP_IRPT_INTR);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}

XHwIcap_SetInterruptHandler(&HwIcap,&HwIcap, (XHwIcap_StatusHandler)HwIcapIntrHandler);

print("\n");
//XHwIcap_Reset(&HwIcap);
Status=XHwIcap_DeviceWrite(&HwIcap,(u16 *)&ConfigRegData16[0],14);

while(TransferInProgress);
return Status;
}

void HwIcapIntrHandler(void *CallBackRef, u32 StatusEvent, u32 ByteCount)
{
/*
* Indicate the transfer between the HwIcap to the Icap device is done
* regardless of the status event.
*/
TransferInProgress = FALSE;

/*
* If the event was not transfer done, then track it as an error.
*/
if (StatusEvent != XST_HWICAP_WRITE_DONE) {
Error++;
}
}

static int HwIcapSetupInterruptSystem(XIntc* IntcInstancePtr,
XHwIcap *HwIcapPtr,
u16 IntrId )
{
int Status;

/*
* Initialize the interrupt controller driver so that it's ready to use.
*/
Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}

/*
* Connect the handler that will be called when an interrupt
* for the device occurs, the handler defined above performs the
* specific interrupt processing for the device.
*/
Status = XIntc_Connect(IntcInstancePtr,
IntrId,
(XInterruptHandler) XHwIcap_IntrHandler,
HwIcapPtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}

/*
* Start the interrupt controller so interrupts are enabled for all
* devices that cause interrupts. Specify real mode so that the
* HwIcap device can cause interrupts through the interrupt
* controller.
*/
Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}

/*
* Enable the interrupt for the HwIcap device.
*/
XIntc_Enable(IntcInstancePtr, IntrId);

/*
* Initialize the exception table.
*/
Xil_ExceptionInit();

/*
* Register the interrupt controller handler with the exception table.
*/
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler) XIntc_InterruptHandler,
IntcInstancePtr);

/*
* Enable non-critical exceptions.
*/
Xil_ExceptionEnable();

return XST_SUCCESS;
}
code for switching the bit stream is spi flash.fpga application will switch tha bitstream images.use this code icap is working fine and fpga is reconfigured at run time
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Observer thathunu13
Observer
9,312 Views
Registered: ‎07-10-2014

Re: spartan-6 ICAP configuration

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hello kishore, 

 

can i get this code in VHDL? please

 

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Visitor lalitha
Visitor
6,542 Views
Registered: ‎03-14-2016

Re: spartan-6 ICAP configuration

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hello,

 I am little bit confused when i am working with HW_ICAP driver, from where does the icap get the address of the next image. If the hw_icap driver get the address from  this sequence

static u32 sequence [HWICAP_bitstreamlength]=

{

FFFFFFFF,

AA995566,

31E1FFFF,

32610000,

32810320,

....

...

30A1000E,

20002000,

};

then what is  the need of header file which will contain the same set of commands ( as in that of sequence).And how the header get interacts with the multiboot and fall back image (ie) how significant the header is. 

 

 

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Xilinx Employee
Xilinx Employee
6,498 Views
Registered: ‎07-21-2014

Re: spartan-6 ICAP configuration

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Hi,

Header is basically important for fallback operation.
Please open a new thread for your question about this issue for further discussion as it seems the original question is already marked as solution. You will get immediate attention about this over new thread.

-Shreyas
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Try to search answer for your issue in forums or xilinx user guides before you post a new thread.

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Visitor lalitha
Visitor
6,493 Views
Registered: ‎03-14-2016

Re: spartan-6 ICAP configuration

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Hi,

  Thanks for the reply this is my new post link is  https://forums.xilinx.com/t5/Welcome-Join/Spartan-6-ICAP-configuration-issue/td-p/687854.since its blocking my project ,im seeking for the solution.

 

-Lalitha

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