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ame
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Registered: ‎09-24-2019

using assert

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Hello, I try to use assert to create a self verification testbench of a count 8 bit, but I face a question. assert condition is right but it report error message yet. Could anyone tell me what's the problem?

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testbench of counter 8 bit(assert underlined)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity test_additionneur_2N is

end;
architecture test_bench of test_additionneur_2N is
constant Nbit: integer:= 4;
type sample_array is array(7 downto 0) of unsigned(2*Nbit-1 downto 0);
constant test_data : sample_array:=
(
"00000000",
"00000001",
"00000010",
"00000011",
"00000100",
"00000101",
"00000110",
"00000111"
);
signal clk, rst : std_logic;
signal result:unsigned(2*Nbit-1 downto 0);
begin
process
begin
rst<='1';
for i in 1 to 5 loop
clk<='0';
wait for 5 ns;
clk<='1';
wait for 5 ns;
end loop;
rst<='0';

for i in test_data'range loop
clk<='0';
wait for 5 ns;
clk<='1';
wait for 5 ns;


assert result = test_data(i);
report "result: expect="&to_string(to_integer(result))&
",actual="&to_string(to_integer(test_data(i)))
severity error;
end loop;
wait;
end process;

CUT:entity work.additionneur_2N port map(clk,rst,result);

end;

 

 if nececessary , ip of counter:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity additionneur_2N is
generic ( Nbit: integer:= 4
);
port ( clk : in std_logic;
rst : in std_logic;
result : out unsigned(2*Nbit-1 downto 0));
end;

architecture behaviour of additionneur_2N is
signal reg_high,reg_low,next_high_result,next_low_result,reg_low_delay : unsigned(Nbit-1 downto 0);
signal high_bit: integer;
begin
high_addtion: next_high_result<=high_bit+reg_high;
low_addtion: next_low_result<=1+reg_low;
--low_to_high: high_bit<=1 when to_integer(next_low_result)=1 else 0;
combine_result: result<=reg_high&reg_low_delay;

low_to_high:process(clk)
begin
if rising_edge(clk) then
if rst='1' then
high_bit<=0;
elsif to_integer(next_low_result)=0 then
high_bit<=1;
else
high_bit<=0;
end if;
end if;
end process;

fifo:process(clk)
begin
if rising_edge(clk) then
if rst='1' then
reg_high<=(others=>'0');
reg_low<=(others=>'0');
reg_low_delay<=(others=>'0');
else
reg_high<=next_high_result;
reg_low<=next_low_result;
reg_low_delay<=reg_low;
end if;
end if;
end process;

end architecture;

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Accepted Solutions
richardhead
Scholar
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429 Views
Registered: ‎08-01-2012

The error is an erroneous semi colon

richardhead_0-1611935894732.png

Here, you break the assert into one statement, and the report into another (they are perfectly legal statements without each other).

So, remove the ;

View solution in original post

9 Replies
drjohnsmith
Teacher
Teacher
571 Views
Registered: ‎07-09-2009

Counter intuitively  i know ,

   but assert is triggered on a negative ( i.e. false ) 

 

  https://www.ics.uci.edu/~jmoorkan/vhdlref/assert.html

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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ame
Contributor
Contributor
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Registered: ‎09-24-2019

normally when condition "result = test_data(i)" is wrong, it will print the error message, but as you can see, the values are same in the printed message, so I'm confused with it. 

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richardhead
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Registered: ‎08-01-2012

Have you checked that "result" contains all 0 or 1 values? If there are any meta values in the array, it will fail the compare. But to_integer will convert any 'U' or 'X' values to 0 (this throws a warning in numeric_std that most people turn off in the settings).

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

remeber VHDL is striclty typed,

  As @richardhead said, meta data can cause problems

      also things like if you compare a 7 bit number to a 6 bit one, it will always be false

        I'm not certain about comparing a value from an array, against a signal, 

           may be try casting them both to the same size / type 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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richardhead
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Registered: ‎08-01-2012

@drjohnsmith 

Length missmatch is not a problem when doing arithmetic compares. Doing compares between two unsigned will ignore the length and only compare numerically. This is because the overloaded "=" function in numeric_std (and std_logic_unsigned and numeric_std_unsigned) convert both operands to the length of the longer one first. The implicit "=" function for all array types will always missmatch when the lengths differ (hence why compares of two SLVs will always fail when the lengths dont match when only using std_logic_1164).

There is no problem matching against an array element, because both sides of the "=" function are unsigned (otherwise you would get a type missmatch etc).

 

ame
Contributor
Contributor
449 Views
Registered: ‎09-24-2019

Well, it's all '1' and '0', so I have no idea about the errorScreenshot 2021-01-29 202538.PNG.jpg

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richardhead
Scholar
Scholar
430 Views
Registered: ‎08-01-2012

The error is an erroneous semi colon

richardhead_0-1611935894732.png

Here, you break the assert into one statement, and the report into another (they are perfectly legal statements without each other).

So, remove the ;

View solution in original post

ame
Contributor
Contributor
396 Views
Registered: ‎09-24-2019

Thank you, it works.

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ame
Contributor
Contributor
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Registered: ‎09-24-2019

And thank you for your help.

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