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Registered: ‎03-02-2020

what is Configuration Memory mentioned in PG036?

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Hi, I'm reading PG036, and is puzzled that what is the mentioned Configuration Memory in page 5? Below is the description: Configuration Memory: Storage elements used to configure the function of the design loaded into the device. This includes function block behavior and function block connectivity. This memory is physically distributed across the entire device and represents the largest number of bits. Only a fraction of the bits are essential to the proper operation of any specific design loaded into the device. I guess it could not be the external Flash used for configuration. But in my opinion, after power-up and LUT initialization is done, it seems don't need the "Configuration Memory" any more until next power up. So even there is soft-error in the Configuration Memory, it won't interfere the normal functon of FPGA, and after next power-up FPGA will be re-configured by the external flash, also no influnce on the FPGA. So why need to diagnose Configuration Memory using SEM IP? Actually I don't know much about FPGA architecture, and maybe this is a stupid question, but it means much for me to perform safety analysis. So looking forward for your reply and thank you so much.
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Registered: ‎01-22-2015

Re: what is Configuration Memory mentioned in PG036?

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@ycsy2219 

     So can I regard it as that CCLs determins the function of each slices?
Yes, although we more often say that the CCLs determine function of the Configurable Logic Blocks (CLBs) – see Chapter 1 of UG474.

Please note that the CCLs are volatile memory.  That is, when the FPGA is powered down then the CCLs lose their settings.  –and, when you power-up the FPGA it is not configured until configuration data is written to the CCLs.  Some early FPGAs (eg. Spartan-3AN) from Xilinx had internal flash (non-volatile) memory that could be used to store the FPGA configuration.  However, at power-up of the FPGA, the FPGA transferred the contents of internal flash to the CCLs in order to configure itself.

 

     So if there are errors in CCLs, the coresponding slice will not act in a correct way immediately?
As you will read in PG036, there are essential and non-essential bits in the CCLs.  If a non-essential bit is corrupted then there is no impact to function of the CLBs.  It is my understanding that when an essential bit is corrupted then function of the CLB is affected immediately. 

As described in PG036, the SEM can use the “replace method” to correct an error in a CCL essential bit.  That is, the SEM obtains the correct value for the essential bit from a copy of the FPGA configuration data and writes this correct value to the CCL.  In chapter 2 of PG036, you will see tables of error correction latency times.   As shown in Fig 1-1 of PG036, SEM error correction must sometimes be accompanied by a reset of the programmable logic application.

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Registered: ‎01-22-2015

Re: what is Configuration Memory mentioned in PG036?

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@ycsy2219 

Welcome!

Xilinx FPGA configuration data is stored in CMOS configuration latches (CCLs) that are located internal to the FPGA.   These CCLs are the configuration memory referred to in PG036.

As explained <here>, you can think of the FPGA as a hierarchy of "reconfigurable interconnects" that allow digital circuit blocks to be "wired together".  The data stored in the CCLs determines how the "reconfigurable interconnects" (aka switches) are set.  

If data in the CCLs becomes corrupted then the "reconfigurable interconnects" are switched the wrong way and the FPGA fails to work properly.  PG036 tells you how to use SEM to detect corrupted data in the CCLs.

Cheers,
Mark

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Re: what is Configuration Memory mentioned in PG036?

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Thanks for your rapid reply. So can I regard it as that CCLs determins the function of each slices? So if there are errors in CCLs, the coresponding slice will not act in a correct way immediately?
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Registered: ‎01-22-2015

Re: what is Configuration Memory mentioned in PG036?

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@ycsy2219 

     So can I regard it as that CCLs determins the function of each slices?
Yes, although we more often say that the CCLs determine function of the Configurable Logic Blocks (CLBs) – see Chapter 1 of UG474.

Please note that the CCLs are volatile memory.  That is, when the FPGA is powered down then the CCLs lose their settings.  –and, when you power-up the FPGA it is not configured until configuration data is written to the CCLs.  Some early FPGAs (eg. Spartan-3AN) from Xilinx had internal flash (non-volatile) memory that could be used to store the FPGA configuration.  However, at power-up of the FPGA, the FPGA transferred the contents of internal flash to the CCLs in order to configure itself.

 

     So if there are errors in CCLs, the coresponding slice will not act in a correct way immediately?
As you will read in PG036, there are essential and non-essential bits in the CCLs.  If a non-essential bit is corrupted then there is no impact to function of the CLBs.  It is my understanding that when an essential bit is corrupted then function of the CLB is affected immediately. 

As described in PG036, the SEM can use the “replace method” to correct an error in a CCL essential bit.  That is, the SEM obtains the correct value for the essential bit from a copy of the FPGA configuration data and writes this correct value to the CCL.  In chapter 2 of PG036, you will see tables of error correction latency times.   As shown in Fig 1-1 of PG036, SEM error correction must sometimes be accompanied by a reset of the programmable logic application.

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Re: what is Configuration Memory mentioned in PG036?

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Thanks a lot! Have a nice day!

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