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10,616 Views
Registered: ‎08-25-2015

write_cfgmem command not generating Multi-boot Mcs

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Hi,

 

I have a problem in Vivado 2014.2 when i try to create an .mcs with the following command:

 

write_cfgmem -format mcs -interface SPIX4 -size 32 -loadbit "up 0 D:/multi_boot/bit_files/multi_boot_golden.bit up
0x01000000 D:/multi_boot/bit_files/multi_boot_update.bit" D:/multi_boot/bit_files/golden.mcs

 

 

 

ERROR: [Vivado 12-3740] The SPIX4 interface does not support daisy chaining bit files.

 

I would like to know where is the error i am committing? I would like to know is it the proper way to generate the mcs for multiboot.

 

Thank you,

K Nagarjuna

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pratham
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Registered: ‎06-05-2013

nagarjuna.k@mistralsolutions.com Great! please close this thread

-Pratham

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pratham
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nagarjuna.k@mistralsolutions.com You need to apply all SPI releated constraint.

 

Apply all constraint and rerun bitstream.

-Pratham

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balkris
Xilinx Employee
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Registered: ‎08-01-2008

elow is the procedure to boot a 'Peripheral Test' application from a serial flash using the SPI SREC bootloader based MCS image. 

  1. Create an SPI SREC bootloader application from SDK.
     
  2. In SREC bootloader application sources, change the address in blconfig.h:
     
    #define FLASH_IMAGE_BASEADDR  <offset of the SREC image to be programmed to flash>
     
    For example, if the flash base address in the Vivado project (check the address editor) is 0xC2000000 and you want to give an offset of 0x00C00000 then the value of FLASH_IMAGE_BASEADDR will be 0x00C00000
     
  3. Change the BSP settings Include the xilisf (Xilinx In-system and Serial Flash Library)
     
  4. Rebuild the application.
     
  5. Now create one more application, for example Peripheral Test from SDK - link to DDR (in the linker script make sure that this application is executing from DDR)
     
  6. Convert the generated Peripheral Test elf into SREC format (mb-objcopy -O srec <elf> <srec>)
     
  7. Convert the Peripheral SREC file to MCS format, using write_cfgmem in Vivado (offset of the SREC file in MCS should be the offset specified in the blconfig.h)
     
    For the above case where FLASH_IMAGE_BASEADDR is 0xC2C00000, the command to create peripheral_test.mcs file would be:
     
    write_cfgmem -format mcs -size 128 -checksum FF -interface spix4 -loaddata "up 0x00C00000 /path/to/peripheral_test.srec" -force peripheral_test
     
  8. Use Vivado to program the peripheral_test.mcs file onto the flash
    (Note: In 2015.1 SDK, You can create the MCS files from bootgen and SDK also supports programming SPI flashes as well --> Still in test phase)
     
  9. Use SDK to create a download.bit from system.bit by using Program FPGA
     
  10. Select Bitstream (system.bit) and the ELF file to initialize BRAM (srec bootloader elf built in step 5)
     
  11. Program the FPGA
     
  12. Once the FPGA is configured, the SREC bootloader runs, copies the image from flash to DDR, and executes Peripheral Test application.





Note: In step 8, you can also add the download.bit (that would be created in step 11) to create a monolithic mcs image that will configure the FPGA as well as load the user application. 

write_cfgmem -format mcs -size 128 -checksum FF -interface spix4 -loaddata "up 0x0 /path/to/download.bit up 0x00C00000 /path/to/peripheral_test.srec" -force peripheral_test

 

Also, do not forget to select the appropriate value for serial_flash_family  (based on the type of serial flash you have) and serial_flash_interface in the BSP settings of the SPI SREC Bootloader:
 



 

Thanks and Regards
Balkrishan
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balkris
Xilinx Employee
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Registered: ‎08-01-2008

To correctly generate BIN or MCS in SPIx4 or SPIx2 mode, bitstream property "SPI_BUSWIDTH" should have been set properly in the bit file:

set_property BITSTREAM.Config.SPI_BUSWIDTH 4 [current_design]
 
One way is to add the Tcl command into .xdc and rerun implementation.
 
Another more convenient way without rerunning is to open the implemented design, and put the following commands in Tcl console successively:
    1.set_property BITSTREAM.Config.SPI_BUSWIDTH 4 [current_design]
    2.write_bitstream xxx.bit (make sure do not click "Generate Bitstream" button instead)
    3.write_cfgmem -format mcs -interface SPIx4 -size xxx -loadbit "up 0x0 xxx.bit" -file xxx.mcs
 
The mcs file should be generated sucessfully.

 

Thanks and Regards
Balkrishan
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10,592 Views
Registered: ‎08-25-2015

 Hi,

Thank you for reply.

I have already applied the following constraints for Golden Bitstream:

 

set_property BITSTREAM.CONFIG.CONFIGRATE 26 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x01000000 [current_design]

set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 32'h00000000 [current_design]

 set_property BITSTREAM.CONFIG.NEXT_CONFIG_REBOOT ENABLE [current_design]

 

and for generating updated bit stream

 

 

set_property BITSTREAM.CONFIG.CONFIGRATE 26 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
#set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x01000000 [current_design]


set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 32'h00000000 [current_design]

 


set_property BITSTREAM.CONFIG.NEXT_CONFIG_REBOOT DISABLE [current_design]

 

as recommended in the http://www.xilinx.com/support/documentation/application_notes/xapp1247-multiboot-spi.pdf

 

Awaiting suggestions,

 

 

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pratham
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nagarjuna.k@mistralsolutions.com Do you have  these constraints? 

 

Example:

 

set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 2.5 [current_design]

 

I dont know why this constraint?

 

set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 32'h00000000 [current_design]

 

 

-Pratham

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pratham
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nagarjuna.k@mistralsolutions.com Did that work? Let us know if you still have issue

-Pratham

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10,486 Views
Registered: ‎08-25-2015

Thank you Pratam,

 

Issue is with Vivado tool. That Multiboot .mcs with two bit file which is used for Remote Reconfiguring can be generated with the new Vivado version 2015.1.

 

The constraints you said also added now.

Now tool has generated the .mcs as mentioned in the xapp1247.

 

 

Thank you..... 

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pratham
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nagarjuna.k@mistralsolutions.com Great! please close this thread

-Pratham

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View solution in original post

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mamisadegh3
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Registered: ‎09-19-2010

Hi

 

I have a Kintex7 board with QSPI flash, and the multiboot does not work.

 

I am using vivado 2015.2 and my configuration is exactly similar to the above.

The same config works for my Virtex7 design perfect.

 

For Kintex7 , I create the mcs file containing both of the Golden and main image and program the spi flash with vivado.

 

Then, when I turn the card on, I always see that the fall back happens with watch dog timer error.

This mean jump has happened, but loading the main image always gets timed out!

I have checked the generated mcs file and I am sure the main image it there.

I have tried the main image alone, and it loads in less than 2 seonds. The value i have defined for watchdog timer is 10 seconds.

 

After two days of fighting, I am now completely out of ideas.

Any idea is really appreciated!

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nmartinez
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Registered: ‎07-19-2020

I just discovered this issue using vivado version 2019.1. I have 2 laptops one is running windows 8 2019.1 and the other one has windows 10 2019.1. When I ran the command below in the windows 10 laptop, I get the following

write_cfgmem -format mcs -size 16 -interface SPIx4 -loadbit "up 0x00000000 Diality_top-golden.bit
up 0x00240000 Diality_top-update.bit" -loaddata "up 0x0023FC00 timer1.bin up 0x00480000
timer2.bin" Diality_top.mcs
Command: write_cfgmem -format mcs -size 16 -interface SPIx4 -loadbit {up 0x00000000 Diality_top-golden.bit
up 0x00240000 Diality_top-update.bit} -loaddata {up 0x0023FC00 timer1.bin up 0x00480000
timer2.bin} Diality_top.mcs
Creating config memory files...
Creating bitstream load up from address 0x00000000
ERROR: [Writecfgmem 68-24] The SPIX4 interface does not support daisy chaining bit files.
0 Infos, 0 Warnings, 0 Critical Warnings and 1 Errors encountered.
write_cfgmem failed
ERROR: [Common 17-39] 'write_cfgmem' failed due to earlier errors.

But when I ran in the windows 8 laptop. The exact same command runs perfectly fine.

These are the addresses that outputs the command along with the output file.

Addr1 Addr2 Date File(s)
0x00000000 0x0021728B Jul 19 12:28:32 2020 Diality_top-golden.bit
0x0023FC00 0x0023FFFF Jul 19 10:53:22 2020 timer1.bin
0x00240000 0x0045728B Jul 19 12:45:12 2020 Diality_top-update.bit
0x00480000 0x0048003B Jul 19 10:53:22 2020 timer2.bin

 

Any suggestions??

 

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