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Observer
Observer
520 Views
Registered: ‎06-07-2018

zynq 7007s FPGA clock

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i'm unable to configure the FPGA clock 2 and 3.

FPGA clock 0 and 1 are working fine.

 

does this part support FPGA clock 2 and 3 ?

if so what is the register programming sequence for enabling those ?

i have already tried writing to the FPGAx_CLK_CTRL.

FPGAx_THR_STA is 0x00010000 for FPGA clk 0 and 1 but it is at 0x00000000 for FPGA clk 2 and 3

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Adventurer
Adventurer
410 Views
Registered: ‎05-23-2018

Just regenerate the bsp and compare the ps7_init.c to the one of your previous build. 

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Xilinx Employee
Xilinx Employee
496 Views
Registered: ‎11-05-2019

 

Hello @prasanth_s 

 

You may not have changed the configuration of FCLK2 and 3.

Capture.PNG

 

Thanks

Yoichi

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Observer
Observer
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Registered: ‎06-07-2018

i have changed configuration in the vivado.

it is after this i'm having the problem.

additional information : using petalinux

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Adventurer
Adventurer
475 Views
Registered: ‎05-23-2018

Have you reexported and regenerated everything? Especially FSBL/bsp.

 

These configurations go to all the registers in the PS and are usually set up by the FSBL in ps7_init. 

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Observer
Observer
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Registered: ‎06-07-2018

which registers are to be programmed at what sequence to enable the clocks ?

i do not want to re-export and regenerate the linux as i have to add back all the user apps and other stuffs to the compilation.

we prefer a simpler solution of the register progamming sequence

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Adventurer
Adventurer
411 Views
Registered: ‎05-23-2018

Just regenerate the bsp and compare the ps7_init.c to the one of your previous build. 

View solution in original post

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Observer
Observer
334 Views
Registered: ‎06-07-2018

i had to write a 0x0 to "FPGAx_THR_CNT" in addition to the registers and values in the ps7_init.c .

thanks for the guidance on identifying the register values.

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