01-02-2020 10:02 PM
i'm unable to configure the FPGA clock 2 and 3.
FPGA clock 0 and 1 are working fine.
does this part support FPGA clock 2 and 3 ?
if so what is the register programming sequence for enabling those ?
i have already tried writing to the FPGAx_CLK_CTRL.
FPGAx_THR_STA is 0x00010000 for FPGA clk 0 and 1 but it is at 0x00000000 for FPGA clk 2 and 3
01-03-2020 12:16 AM
You may not have changed the configuration of FCLK2 and 3.
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01-03-2020 01:25 AM
Have you reexported and regenerated everything? Especially FSBL/bsp.
These configurations go to all the registers in the PS and are usually set up by the FSBL in ps7_init.
01-03-2020 01:35 AM
which registers are to be programmed at what sequence to enable the clocks ?
i do not want to re-export and regenerate the linux as i have to add back all the user apps and other stuffs to the compilation.
we prefer a simpler solution of the register progamming sequence
01-06-2020 12:07 AM
i had to write a 0x0 to "FPGAx_THR_CNT" in addition to the registers and values in the ps7_init.c .
thanks for the guidance on identifying the register values.