12-29-2009 10:52 PM
I'm trying to make a pulse generator which generates a pulse every 10 ms. I'm thinking to use a counter but it seems that I might really need to have a large counter with 31.25 ns FPGA clock. Is there any easy way to accomplish this?
12-30-2009 07:43 AM
12-30-2009 01:04 PM
10 ms divided by 31.25 ns is 320000. So even a streight binary counter only needs to be 19 bits long, which is eaqsy in all but the smallest of cplds.
just count 0 to 4E1FF hex and wrap back to 0. gen a pulse on the wrap.
12-30-2009 02:45 PM
You might consider using an LFSR counter, which requires less logic to implement.
Here is an online LFSR counter generator:
Hope that helps
That's a pretty neat program. One other method that helps in CPLD's is to decode the end state
serially. One of the problems with many CPLD's is the limit of the number of inputs to each
block of macrocells. LFSR counters help reduce this over a binary counter, because each bit
only relies on the previous bit in the shift register, except for the XOR bit which should not
need more than 4 inputs for a maximal length count. However if you need to count by some
other number and need to restart at a particular count, a parallel equality comparator needs
all of the bits of the register at once, which negates the gain in terms of inputs to a macrocell
block. However because the state is contained in a simple shift register, you can use a
state machine to detect the end state (this is easiest if your end state is all ones or all zeroes)
using a single bit from the shift register. For very long LFSR's this method reduces logic
significantly. The fun part is determining the starting state of the LFSR to load when you
detect all ones (or all zeroes) to get the length you need.