cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
hpoetzl
Voyager
Voyager
12,386 Views
Registered: ‎06-24-2013

12bit SERDES with ISERDESE2 (7series) possible?

Is there an actual reason why a master-slave setup of two ISERDESE2 primitives can handle 10 and 14 bit but not 12 bit?

 

I can see that a 16 bit mode is not possible as the slave version starts with Q3 instead of Q1, but why is a 12 bit mode a problem?

 

Thanks in advance,

Herbert

-------------- Yes, I do this for fun!
0 Kudos
37 Replies
rickwen77
Visitor
Visitor
2,794 Views
Registered: ‎09-02-2016

@samcossais,this is very helpful for my design. I was wondering whether there is a workaround for 12bit OSERDESE2?

0 Kudos
samcossais
Scholar
Scholar
2,768 Views
Registered: ‎12-07-2009

No idea but the workaround I mentionned here might work symmetrically for output. Or maybe 12b OSERDESE2 just works with the native cascade setup, I don't know. I never use OSERDES. Is it a fast signal you have to output ?

0 Kudos
whelm
Explorer
Explorer
2,748 Views
Registered: ‎05-15-2014

I haven't tried playing with it, but it would seem to me that there should be no need to tell it how many bits, other that related to whether one or two serdes are required.  I would think that setting it to 14 would work for 12 or 10 as well, just fine, as long as the frame clock was 1/6 (12 bit DDR) or whatever of the bit clock.  I would presume the implementation is a double buffered combination of shift register and holding register.  It isn't obvious why fewer shift clocks before a load clock would make any difference to the hardware.  Am I missing something?  There would obviously be "don't care" bits in the output, but they don't even have to be routed to anything.

 

0 Kudos
samcossais
Scholar
Scholar
2,657 Views
Registered: ‎12-07-2009

It makes sense to think so in my opinion too. I don't remember well but I think that in practice setting the wrong number doesn't work though.

0 Kudos
svenn
Contributor
Contributor
2,622 Views
Registered: ‎03-04-2009

Push Xilinx support to get the latest version of xapp524 from Marc. He has done some modifications.

I asked for help to get xapp524 to synthezise for 12-bit and I posted some modifications to the original xapp524 here:

https://forums.xilinx.com/t5/7-Series-FPGAs/xapp524-12-bit-1-wire-mode-will-not-synthezise/m-p/561375

0 Kudos
samcossais
Scholar
Scholar
2,613 Views
Registered: ‎12-07-2009

He has not answered for a very long time, I would not be surprised if Marc was not working at Xilinx anymore (I hope he still does though).

0 Kudos
Kalpitha24
Newbie
Newbie
204 Views
Registered: ‎05-11-2021

 Hello Samcossias,

 

What if I have to make use of OSERDES2, 12 bit. Since I have to send a serial data over the LVDS output pair?

 

 

 

 

0 Kudos
samcossais
Scholar
Scholar
148 Views
Registered: ‎12-07-2009

Hello,

I am not sure if I understand your question. Do you mean you want to know if you should use OSERDES if you need to send a serial data over LVDS ? Well I guess if you can then sure you should, it saves you ressources, you don't have to add some severe timing constraints, and it enables higher frequencies. Now if you ask whether it's mandatory or not, then no, or at least it depends on your frequency. If you don't need such a high frequency, and you're struggling using OSERDES (it sure can be tricky sometimes), then you can use ODDR and make your own shift registers using LUTs instead. I think there is some performance data in the data sheet comparing ODDR and OSERDES.

0 Kudos