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Observer
4,043 Views
Registered: ‎02-14-2013

## 2D FIR filter design

Hi,

I want to design a 2D FIR filter with frequency response having magnitude 1 and negative linear phase(exp(-jwt) in xilinx FPGA. Can I get some suggestions?

Thank you

1 Solution

Accepted Solutions
Explorer
4,995 Views
Registered: ‎07-06-2008

@neera84 wrote:

Hi,

I want to design a 2D FIR filter with frequency response having magnitude 1 and negative linear phase(exp(-jwt) in xilinx FPGA. Can I get some suggestions?

Thank you

An FIR filter is charecterised by its coefficients. You need to find the coefficients for a practical design (not too many taps) first by doing some calculation, plugging some values into equations that could be standard formulae for filter design (Butterworth, Chebyshev etc.) or maybe you could come up with the equations yourself. Once you have the coefficients, you choose the filter's architecture (polyphase etc.) and number representation (fixed point vs. floating point, decimal or CSD). Finally you use a design entry method (schematics or HDL, HDL is by far more practical) to have your design conveyed to the Xilinx tools. You have the option of testing your design in behavioral simulation before you synthesise and implement it.

3 Replies
Explorer
4,996 Views
Registered: ‎07-06-2008

@neera84 wrote:

Hi,

I want to design a 2D FIR filter with frequency response having magnitude 1 and negative linear phase(exp(-jwt) in xilinx FPGA. Can I get some suggestions?

Thank you

An FIR filter is charecterised by its coefficients. You need to find the coefficients for a practical design (not too many taps) first by doing some calculation, plugging some values into equations that could be standard formulae for filter design (Butterworth, Chebyshev etc.) or maybe you could come up with the equations yourself. Once you have the coefficients, you choose the filter's architecture (polyphase etc.) and number representation (fixed point vs. floating point, decimal or CSD). Finally you use a design entry method (schematics or HDL, HDL is by far more practical) to have your design conveyed to the Xilinx tools. You have the option of testing your design in behavioral simulation before you synthesise and implement it.

Teacher
4,021 Views
Registered: ‎11-14-2011

Depending on your level of expertise with filters and design entry with Xilinx, you could use the FIR core from coregen.

Regards,

Howard

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"That which we must learn to do, we learn by doing." - Aristotle
Observer
4,002 Views
Registered: ‎02-14-2013

Thank you