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Visitor rsilvas
Visitor
6,327 Views
Registered: ‎01-19-2010

3.3 ttl to 2.5 ttl?

Hello and thank you in advance for reading. I have a Spartan3AN evaluation board and I wanted to know if the 3.3 output is too much to connect directly to the ML605 evaluation board which takes 2.5V input. I understand that there are level translators that drop the 3.3v to a usable 2.5v but the associated delays with these are not suitable for the speeds I’m going.  So I was wondering if I’m SOL or is there a way I can place a resistor or diode to drop the 3.3v to 2.5v, or if just a direct connection will do. Also I may need to connect a 5v ttl to the Spartan3AN. The speed on this one is not so critical so I could use a level shifter but would like to have a very small delay. Once again I’d like to thank you for your time.

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5 Replies
Scholar austin
Scholar
6,321 Views
Registered: ‎02-27-2008

Re: 3.3 ttl to 2.5 ttl?

r,

 

The Virtex 6 has a protection diode to Vcco (2.5v), so you need at least a hundred ohms or so to limit total current being forced into the Vcco, to less than 100 mA.

 

I would suspect that 150 ohms or so would be sufficient to protect the inputs of hte V6 device from the 3.3v trying to over-current (push up) the 2.5v supply.


If the 2.5v supply is being pushed up, add a load across it to pull it down.

 

Stay within the abs max specifications, don't inject more than 100 mA into the Vcco, or ground (per bank, 200 mA total for the whole chip), and make sure the 2.5v supply is not being pushed out of regulation, and everything should be just fine.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Xilinx Employee
Xilinx Employee
6,320 Views
Registered: ‎08-13-2007

Re: 3.3 ttl to 2.5 ttl?

Do NOT connect them directly. Assuming you have a nominal 3.3V Vcco supply on S3A and used LVCMOS33 - you will have a nearly 3.3V output there (Voh says it could drop 0.4V - in reality, it is likely much less) which greatly exceeds the Vinmax of V6. See p2 of ds152.

There are some approaches here.

For V6 I would start here:  http://www.xilinx.com/support/documentation/application_notes/xapp899.pdf  (Interfacing Virtex-6 FPGAs with 3.3V I/O Standards)

For 5V into S3A - there is a section called "Using Large-swing signals" in UG331 you should review.

 

bt

 

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Visitor rsilvas
Visitor
6,318 Views
Registered: ‎01-19-2010

Re: 3.3 ttl to 2.5 ttl?

Thank you Austin and Barriet your answers were insightful and helped. Looking into the xapp899.pdf pag e 4 described a totem-pole resistor solution for the V6 3.3v to 2.5v . When I get back to the lab I will setup a test to see if this would be a fix for my problems. Could this solution also be for the 5v to 3.3v, with Vcc=3.3v and Vbias as the 5v input?

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Scholar austin
Scholar
6,315 Views
Registered: ‎02-27-2008

Re: 3.3 ttl to 2.5 ttl?

yes

Austin Lesea
Principal Engineer
Xilinx San Jose
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Instructor
Instructor
6,305 Views
Registered: ‎08-14-2007

Re: 3.3 ttl to 2.5 ttl?

For either the totem pole or the simple series resistor, you should place the resistor(s) as close

as practical to the destination (receiver).  This is because the series resistance will be much

larger than the Zo of the trace and cause a significant slow-down if you place it at the source

(driver) end of the net.  For the totem-pole version you could use lower resistor values, which

could double as a parallel termination (at the cost of increased power).

 

Normally the simple series resistor method is only used for slower signals, as even at the

receiving end of the trace you'll still have the R-C rise time issue due to the large resistance.

Since you mentioned that you didn't want to live with the added delay of signal converters,

I assume you don't want this extra delay.

 

I would normally still recommend active circuits for level-shifting in a high-speed

application, or if possible look into changing Vcco to 2.5V at the Spartan 3 end.

 

-- Gabor

-- Gabor
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