UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer gerstn
Observer
8,212 Views
Registered: ‎09-07-2009

ABEL TO VHDL

Jump to solution

hello,

 

how can I write ABEL Code like this:

 

BR.clk = CK;    // BR is a node register CK is a input pin

BR.ar = RSN;  // RSN is a input pin

 

in VHDL.

 

Thanks for your help

0 Kudos
1 Solution

Accepted Solutions
Instructor
Instructor
10,159 Views
Registered: ‎08-14-2007

Re: ABEL TO VHDL

Jump to solution

Not quite.  The D input part of the equation needs to be inside the process

block in order to happen at the clock edge.  In Abel you just use the := to

indicate at the clock edge.  In VHDL the assignment needs to take place

inside the elsif ...

 

Like:

 

process (CK, RSN)
begin
   if RSN='1' then   
      BR <= '0';
   elsif (CK'event and CK ='1') then

       if BR(6) ='0' then BR <= BR+1;

       else BR<="0000000"; -- in VHDL width of constant has to match width of BR

   end if;
end process;

 

And:

 

process (BR(6), RSN)
begin
   if RSN='1' then   
      UC <= '0';
   elsif (BR(6)'event and BR(6) ='1') then 
      UC <= not UC;
   end if;
end process;

-- Gabor
5 Replies
Highlighted
Instructor
Instructor
8,207 Views
Registered: ‎08-14-2007

Re: ABEL TO VHDL

Jump to solution

You can find this in the language templates included in the ISE GUI.  What you're

describing in Abel is a flip-flop with an asynchronous clear input.  Normally you'd also

have an equation for the D input of your flip-flop.

 

-- Usage of Asynchronous resets may negatively impact FPGA resources
-- and timing. In general faster and smaller FPGA designs will
-- result from not using Asynchronous Resets. Please refer to
-- the Synthesis and Simulation Design Guide for more information.
process (<clock>, <reset>)
begin
   if <reset>='1' then  
      <output> <= '0';
   elsif (<clock>'event and <clock>='1') then
      <output> <= <input>;
   end if;
end process;

In the above code, <output> could be replaced with BR,

<input> would be whatever goes to BR.d, <reset> could be RSN, and

<clock> would be CK.  Note that this code generates an active

high reset input.  RSN seems to imply an active low signal, but your

Abel code doesn't seem to bear this out.  The language templates

also have standard templates for flip-flops with asynchronous

presets and clock enables in all combinations of rising and falling

edge and active high or low inputs.

-- Gabor
0 Kudos
Observer gerstn
Observer
8,203 Views
Registered: ‎09-07-2009

Re: ABEL TO VHDL

Jump to solution

Hey thanks for your help!!

 

If I understand your description the following Abel Code:

 

when !BR6 then BR := BR +1
 else        BR := 0 ;
   BR.CLK = CK;
   BR.AR = RSN;
 UC := !UC;
   UC.CLK = BR6;
   UC.AR = RSN;

 

is the same as this in VHDL

 

if BR(6) ='0' then BR <= BR+1;

elsif BR<='0';

process (CK, RSN)
begin
   if RSN='1' then   
      BR <= '0';
   elsif (CK'event and CK ='1') then 
      BR <= BR;
   end if;
end process;

 

0 Kudos
Observer gerstn
Observer
8,202 Views
Registered: ‎09-07-2009

Re: ABEL TO VHDL

Jump to solution

sorry I forgot 

 

UC <= NOT UC;

process (BR(6), RSN)
begin
   if RSN='1' then   
      UC <= '0';
   elsif (BR(6)'event and BR(6) ='1') then 
      UC <= UC;
   end if;
end process;

 

thanks for your reply

0 Kudos
Instructor
Instructor
10,160 Views
Registered: ‎08-14-2007

Re: ABEL TO VHDL

Jump to solution

Not quite.  The D input part of the equation needs to be inside the process

block in order to happen at the clock edge.  In Abel you just use the := to

indicate at the clock edge.  In VHDL the assignment needs to take place

inside the elsif ...

 

Like:

 

process (CK, RSN)
begin
   if RSN='1' then   
      BR <= '0';
   elsif (CK'event and CK ='1') then

       if BR(6) ='0' then BR <= BR+1;

       else BR<="0000000"; -- in VHDL width of constant has to match width of BR

   end if;
end process;

 

And:

 

process (BR(6), RSN)
begin
   if RSN='1' then   
      UC <= '0';
   elsif (BR(6)'event and BR(6) ='1') then 
      UC <= not UC;
   end if;
end process;

-- Gabor
Observer gerstn
Observer
8,166 Views
Registered: ‎09-07-2009

Re: ABEL TO VHDL

Jump to solution

Ahh OK thanks a lot!!! Maybe I will have a question to my further work. Am I allowed to write you a pn if this happens ? :)

 

 

 

 

0 Kudos