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Visitor
Visitor
8,719 Views
Registered: ‎05-08-2008

AXI_DMA S2MM Interrupt

Hi there

 

Recently I’ve been studying how to use AXI_DMA core with ZedBoard. I’m using s2mm channel to transfer data to DRAM in scatter gather mode.

The block diagram is showed in the picture below (it based on the example of Mohammadsadegh Sadri Zynq training course. Thank him).

axi_dma_samplegenerator.PNG

I took the Xilinx example as software reference and finally I can get this stuff somehow work, which means the number of packets I got is correct and also when I look into my DRAM area (RX BUFFER), the data there is as expected. The Packet size is smaller than the RX buffer size, so that I can make sure, that only one descriptor per packet is needed.

However one thing I still can’t make it work is that I would like to have ONE INTERRUPTION PER EACH PACKET received instead of ONE INTERRUPTION PER BD RING. I went through the axi dma document and explicitly using the XAxiDma_BdRingSetCoalesce(RxRingPtr, 1,0) to ask the dma core to interrupt every packet, but it doesn’t work….In fact, it seems it has no effect at all, because no matter what number I put there, it always one interrupts per BD Ring….

 

It would be very apprechiated if some one could explain me why is that.

 

p.s if some one would like to look into the code in detail, please just email me.

 

Thanks a lot.

 

Vicky

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Xilinx Employee
Xilinx Employee
8,657 Views
Registered: ‎08-02-2011

Hi Vicky,

 

Hmm, that seems strange. What's the value of the IRQThreshold bits of the S2MM_DMACR right before you kick off the DMA?

 

You might find these helpful:

http://www.xilinx.com/support/answers/57550.html

 

Specifically this one:

http://www.xilinx.com/support/answers/58080.html

www.xilinx.com
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Visitor
Visitor
8,583 Views
Registered: ‎05-08-2008

Dear Xilinx,

 

thank you very much for your quick reply.

 

the example you recommended I've checked before I did this post. I checked both Hardware design in Vivado and the software design as reference. I didn't found anything unusual compared to my design. Maybe I missed something….

 

I checked the S2MM_DMACR right before I kick off the DMA(XAxiDma_BdRingStart(RxRingPtr)) by using two ways:

1. XAxiDma_BdRingGetCoalesce(RxRingPtr,*Counter,*Delay)

This gives me *counter=1,*Delay=0;

 

2. Rx_DMACR=XAxiDma_ReadReg(RxRingPtr->ChanBase,XAXIDMA_CR_OFFSET)

This gives me 0x17002. As you can tell this is consistent with the first read approach.

 

Maybe there is something wrong with my read back or seeting approch? Is the information RxRingPtr sufficient to set/get the Coalesce? Because I noticed, that the register offset is 30h for s2mm channel instead of  00h for mm2s channel. I tend to think, the offset of the resiger is automacticly ajusted accrording to the type of the channel(Rx or Tx). Isn't it?

 

 

Thanks in advance.

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Xilinx Employee
Xilinx Employee
8,544 Views
Registered: ‎08-02-2011

Hmmm, that's a good point. Reading through the driver, it is using RxRingPtr->ChanBase just like you are and expects it to be appropriately offset for S2MM vs MM2S. It wouldn't hurt to verify this, though. Either run the debugger and check the value in the 'Variables' window or just use xmd (mrd command) to directly read the value of S2MM_DMACR.

www.xilinx.com
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Visitor
Visitor
8,367 Views
Registered: ‎05-08-2008

Hello bwiec,

I have checked the register value using mrd during runing the system. it gives me the same answer as 0x17002....

It will be great, if one could look at the code I updated and tell me where I'm doing wrongly.

 

Thanks.

Vicky

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Visitor
Visitor
8,360 Views
Registered: ‎05-08-2008

Hi bwiec,

 

In the attachment is my code. Do you have any other idea, where should I check or where I'm doing wrongly?

 

 

Thanks.

Vicky

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