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Explorer
Explorer
788 Views
Registered: ‎03-29-2017

AXI EthernetLite (LWIP): Write data From FPGA Board to PC Using Python Socket command

Hello, 

        Now i am able to print the data in Hercules, instead i need to print the data in Python Shell. I don`t know anything about Python eventhough i have tried but i am not able to do that. Please apologize me i have posting this query for second time.

 

Without using Hercules, how can i print my data into Shell.

 

I have attached all files even Python Code [But still data is printing in Hercules only]

 

KC_RX_Ethernet.PNG

TCP C Code (XSDK)

 

Main Function



#include <stdio.h>
#include "xparameters.h"

#include "netif/xadapter.h"

#include "platform.h"
#include "platform_config.h"
#if defined (__arm__) || defined(__aarch64__)
#include "xil_printf.h"
#endif

#include "lwip/tcp.h"
#include "xil_cache.h"

#if LWIP_DHCP==1
#include "lwip/dhcp.h"
#endif

/* defined by each RAW mode application */
void print_app_header();
int start_application();
int transfer_data();
void tcp_fasttmr(void);
void tcp_slowtmr(void);

/* missing declaration in lwIP */
void lwip_init();

#if LWIP_DHCP==1
extern volatile int dhcp_timoutcntr;
err_t dhcp_start(struct netif *netif);
#endif


extern int aurora_rx_main();
extern volatile int TcpFastTmrFlag;
extern volatile int TcpSlowTmrFlag;
static struct netif server_netif;
struct netif *echo_netif;

void
print_ip(char *msg, struct ip_addr *ip)
{
    print(msg);
    xil_printf("%d.%d.%d.%d\n\r", ip4_addr1(ip), ip4_addr2(ip),
            ip4_addr3(ip), ip4_addr4(ip));
}

void
print_ip_settings(struct ip_addr *ip, struct ip_addr *mask, struct ip_addr *gw)
{

    print_ip("Board IP: ", ip);
    print_ip("Netmask : ", mask);
    print_ip("Gateway : ", gw);
}

int ProgramSi5324(void);
int ProgramSfpPhy(void);
#endif
#endif
int main()
{

#if __aarch64__
    Xil_DCacheDisable();
#endif

    struct ip_addr ipaddr, netmask, gw;

    /* the mac address of the board. this should be unique per board */
    unsigned char mac_ethernet_address[] =
    { 0x00, 0x0a, 0x35, 0x00, 0x01, 0x02 };

    echo_netif = &server_netif;
#if defined (__arm__) || defined(__aarch64__)
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
    ProgramSi5324();
    ProgramSfpPhy();
#endif
#endif

    init_platform();

#if LWIP_DHCP==1
    ipaddr.addr = 0;
    gw.addr = 0;
    netmask.addr = 0;
#else
    /* initliaze IP addresses to be used */
    IP4_ADDR(&ipaddr,  192, 168,   1, 10);
    IP4_ADDR(&netmask, 255, 255, 255,  0);
    IP4_ADDR(&gw,      192, 168,   1,  1);
#endif    
    print_app_header();

    lwip_init();

      /* Add network interface to the netif_list, and set it as default */
    if (!xemac_add(echo_netif, &ipaddr, &netmask,
                        &gw, mac_ethernet_address,
                        PLATFORM_EMAC_BASEADDR)) {
        xil_printf("Error adding N/W interface\n\r");
        return -1;
    }
    netif_set_default(echo_netif);

    /* now enable interrupts */
    platform_enable_interrupts();

    /* specify that the network if is up */
    netif_set_up(echo_netif);

#if (LWIP_DHCP==1)
    
    dhcp_start(echo_netif);
    dhcp_timoutcntr = 24;

    while(((echo_netif->ip_addr.addr) == 0) && (dhcp_timoutcntr > 0))
        xemacif_input(echo_netif);

    if (dhcp_timoutcntr <= 0) {
        if ((echo_netif->ip_addr.addr) == 0) {
            xil_printf("DHCP Timeout\r\n");
            xil_printf("Configuring default IP of 192.168.1.10\r\n");
            IP4_ADDR(&(echo_netif->ip_addr),  192, 168,   1, 10);
            IP4_ADDR(&(echo_netif->netmask), 255, 255, 255,  0);
            IP4_ADDR(&(echo_netif->gw),      192, 168,   1,  1);
        }
    }

    ipaddr.addr = echo_netif->ip_addr.addr;
    gw.addr = echo_netif->gw.addr;
    netmask.addr = echo_netif->netmask.addr;
#endif

    print_ip_settings(&ipaddr, &netmask, &gw);

    /* start the application (web server, rxtest, txtest, etc..) */
    start_application();

    /* receive and process packets */
    while (1) {
        if (TcpFastTmrFlag) {
            tcp_fasttmr();
            TcpFastTmrFlag = 0;
        }
        if (TcpSlowTmrFlag) {
            tcp_slowtmr();
            TcpSlowTmrFlag = 0;
        }
        xemacif_input(echo_netif);
        transfer_data();
    }
 
    /* never reached */
    cleanup_platform();

    return 0;
}

Echo Function

#include <stdio.h>
#include <string.h>
#include <math.h>
#include <stdlib.h>
#include "ar_rx.h"
#include "lwip/err.h"
#include "lwip/tcp.h"
#if defined (__arm__) || defined (__aarch64__)
#include "xil_printf.h"
#endif


char buf[32] = {0};
extern u32 DestinationBuffer[5];
int transfer_data() {
	return 0;
}
char *itoa(int val, int base){

 int i = 30;
for(; val && i ; --i, val /= base)
buf[i] = "0123456789abcdef"[val % base];
return &buf[i+1];
}
void print_app_header()
{
	xil_printf("\n\r\n\r-----lwIP TCP echo server ------\n\r");
	xil_printf("TCP packets sent to port 6001 will be echoed back\n\r");
}

err_t recv_callback(void *arg, struct tcp_pcb *tpcb,
                               struct pbuf *p, err_t err)
{
	int i,Status;
	Status=aurora_rx_main();
	//xil_printf("%d",DestinationBuffer);
	//u32 rx_fifo_data;

	for(i=0;i<5;i++)
     {
		xil_printf("%d,",DestinationBuffer[i]);
	}
	

	xil_printf("\n");
	    int base=10;
	    char *result={0};
	    char *result1={0};
	    char *result2={0};
	    char *result3={0};
	    char *result4={0};
	    result = itoa(DestinationBuffer[0],base);
	    result1 = itoa(DestinationBuffer[1],base);
	    result2 = itoa(DestinationBuffer[2],base);
	    result3 = itoa(DestinationBuffer[3],base);
	    result4 = itoa(DestinationBuffer[4],base);
	  

	/* do not read the packet if we are not in ESTABLISHED state */
	if (!p) {
		tcp_close(tpcb);
		tcp_recv(tpcb, NULL);
		return ERR_OK;
	}

	/* indicate that the packet has been received */
	tcp_recved(tpcb, p->len);

	/* echo back the payload */
	/* in this case, we assume that the payload is < TCP_SND_BUF */
	if (tcp_sndbuf(tpcb) > p->len) {
		//err = tcp_write(tpcb, p->payload, p->len, 1);
//
		//xil_printf("%s %s",result[0],result[1]);
		err = tcp_write(tpcb,result,2,1);
		err = tcp_write(tpcb,result1,8,1);
		err = tcp_write(tpcb,result2,6,1);
		err = tcp_write(tpcb,result3,2,1);
		err = tcp_write(tpcb,result4,2,1);
	//aurora_rx_main();
	//xil_printf("%c",ascii[0]);




	} else
		xil_printf("no space in tcp_sndbuf\n\r");

	/* free the received pbuf */
	pbuf_free(p);

	return ERR_OK;
}

err_t accept_callback(void *arg, struct tcp_pcb *newpcb, err_t err)
{
	static int connection = 1;

	/* set the receive callback for this connection */
	tcp_recv(newpcb, recv_callback);

	/* just use an integer number indicating the connection id as the
	   callback argument */
	tcp_arg(newpcb, (void*)connection);

	/* increment for subsequent accepted connections */
	connection++;

	return ERR_OK;
}


int start_application()
{
	struct tcp_pcb *pcb;
	err_t err;
	unsigned port = 7;

	/* create new TCP PCB structure */
	pcb = tcp_new();
	if (!pcb) {
		xil_printf("Error creating PCB. Out of Memory\n\r");
		return -1;
	}

	/* bind to specified @port */
	err = tcp_bind(pcb, IP_ADDR_ANY, port);
	if (err != ERR_OK) {
		xil_printf("Unable to bind to port %d: err = %d\n\r", port, err);
		return -2;
	}

	/* we do not need any arguments to callback functions */
	tcp_arg(pcb, NULL);

	/* listen for connections */
	pcb = tcp_listen(pcb);
	if (!pcb) {
		xil_printf("Out of memory while tcp_listen\n\r");
		return -3;
	}

	/* specify callback to use for incoming connections */
	tcp_accept(pcb, accept_callback);

	xil_printf("TCP echo server started @ port %d\n\r", port);

	return 0;
}

Sub-Functions

#include "xparameters.h"
#include "xil_exception.h"
#include "xstreamer.h"
#include "xil_cache.h"
#include "xllfifo.h"
#include "xstatus.h"
#include "xil_printf.h"
#include "ar_rx.h"



#undef DEBUG


XLlFifo FifoInstance;

int aurora_rx_main()
{
	u32 RxWord;
	int Status;
	//xil_printf("Entering RX loop\r\n");
	//while(1)
	{
	Status = XLlFiforx(&FifoInstance, FIFO_DEV_ID);
	if (Status != XST_SUCCESS)
		{
		xil_printf("Axi Streaming FIFO Test Failed\n\r");
		return XST_FAILURE;
		}

	xil_printf("Successfully ran Axi Streaming FIFO \n\r");
	}
	return XST_SUCCESS;

}

int XLlFiforx(XLlFifo *InstancePtr, u16 DeviceId)
{
	//xil_printf("######\n\r");
	XLlFifo_Config *Config;
	int Status,n=0;
	Status = XST_SUCCESS;

	/* Initialize the Device Configuration Interface driver */
	Config = XLlFfio_LookupConfig(DeviceId);
	if (!Config)
	{
		xil_printf("No config found for %d\r\n", DeviceId);
		return XST_FAILURE;
	}

	Status = XLlFifo_CfgInitialize(InstancePtr, Config, Config->BaseAddress);
	if (Status != XST_SUCCESS)
		{
		xil_printf("Initialization failed\n\r");
		return Status;
		}

	while(n<10)
	{
	Status = RxReceive(InstancePtr, DestinationBuffer);

	if (Status != XST_SUCCESS)
				{
		xil_printf("Receiving data failed");
		return XST_FAILURE;
				}
	n++;
	}
	return Status;
}


int RxReceive (XLlFifo *InstancePtr, u32* DestinationAddr)
{

	int i;
	//int Status;
	u32 RxWord;
	static u32 ReceiveLength;

	ReceiveLength = (XLlFifo_iRxGetLen(InstancePtr))/WORD_SIZE;
	
	
	/* Start Receiving */
	if(ReceiveLength>0)
	{
		//xil_printf("@@@@@@@@@ ");

	for ( i=0; i < ReceiveLength; i++)
	{
		RxWord = 0;
		RxWord = XLlFifo_RxGetWord(InstancePtr);

		
		*(DestinationAddr+i) = RxWord;
		//*(DestinationAddr+i) = 10;
		xil_printf("received data : %d\n\r",*(DestinationAddr+i));

	}

	}

return XST_SUCCESS;
}

Header File

u32 DestinationBuffer[5];

#define FIFO_DEV_ID	   	XPAR_AXI_FIFO_0_DEVICE_ID

#define WORD_SIZE 4			/* Size of words in bytes */

#define MAX_PACKET_LEN 4

#define NO_OF_PACKETS 10

#define MAX_DATA_BUFFER_SIZE NO_OF_PACKETS*MAX_PACKET_LEN




int aurora_rx_main();
int XLlFiforx(XLlFifo *InstancePtr, u16 DeviceId);
int RxReceive(XLlFifo *InstancePtr, u32 *DestinationAddr);

PYTHON CODE

import serial.tools.list_ports
list = serial.tools.list_ports.grep('VID:PID=10C4:EA60','hwid')
connected = []
for element in list:
connected.append(element.device)
a=str(connected)
try:
port = connected[0]
baud = 115200
ser = serial.Serial(port, baud, timeout=1)
#input1.encode('UTF-8')
if ser.isOpen():
print(ser.name + ' is open...')
while (1):
out1 = ser.read()
print out1,
ser.close()
except:
pass

 

Thank you in advance

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2 Replies
Observer deeksha@f7
Observer
731 Views
Registered: ‎05-14-2018

Re: AXI EthernetLite (LWIP): Write data From FPGA Board to PC Using Python Socket command

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Explorer
Explorer
705 Views
Registered: ‎03-29-2017

Re: AXI EthernetLite (LWIP): Write data From FPGA Board to PC Using Python Socket command

Thanks for your response. I am new to Ethernet design. So apology me for asking me silly questions.

 

What you said i have tried but i am unable to connect to Terminals like Putty or Tera Terminal.

 

https://forums.xilinx.com/t5/General-Technical-Discussion/EthernetLite-LWIP-Echo-Unable-to-connect-with-Putty-terminal/m-p/896402#M42139

 

https://forums.xilinx.com/t5/Embedded-Development-Tools/KINTEX-KC705-LWIP-Ethernetlite-recv-callback-Function/m-p/896156#M46992

 

Please suggest me. I am really Stuck for past 10 days.

 

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