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wangzhibin
Observer
Observer
5,540 Views
Registered: ‎03-19-2013

AXI VDMA works, but the few lines are not proper, always with paceket loss.

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Hi, all

I met a problem with AXI Video DMA on Zedboard.I am trying to make a simple vdma test demo on zedboard.

Here is my steps.I want to send my own picture(32-bit per pixel) for FPGA processing.
1. I read my own picture to memory and copy them to DDR.
2. Using video dma core to send the input stream from DDR to my own pcore;
3. Samely, recieve the input stream from my pcore to DDR;
4. Finally, Write the output stream from DDR.
But i found the results in the few lines are not proper, always comes with paceket loss?

Any ideas to fix this bug?

 

 When using VDMA  to ransfer an image(32bit per pixel), small image such as 1024*250*32 is OK,  but a larger one such as 1024*1024*32 always comes with packet loss. I think the problem may be the vdma fifo setting.

 

My Project:

project.png

Result Compare

result1.pngresult2.png

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bwiec
Xilinx Employee
Xilinx Employee
6,911 Views
Registered: ‎08-02-2011

I would recommend putting in chipscope on the interconnect and stream sides of VDMA and see if you can spot similar error in the actual hardware. If not, we can narrow it down to the ARM-side setup.

www.xilinx.com

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bwiec
Xilinx Employee
Xilinx Employee
5,536 Views
Registered: ‎08-02-2011
Are you streaming video at this size, or are you only trying to process a single image?
www.xilinx.com
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wangzhibin
Observer
Observer
5,532 Views
Registered: ‎03-19-2013

I only trying to process a single image(32-bit per pixel for test vdma). Really, I want to prcoess the inputstream (256-bit) including five single image.  

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bwiec
Xilinx Employee
Xilinx Employee
6,912 Views
Registered: ‎08-02-2011

I would recommend putting in chipscope on the interconnect and stream sides of VDMA and see if you can spot similar error in the actual hardware. If not, we can narrow it down to the ARM-side setup.

www.xilinx.com

View solution in original post

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wangzhibin
Observer
Observer
5,508 Views
Registered: ‎03-19-2013

Thanks for your tips, I have fixed the bug. I remove the hdmi output driver, because it always moniter the AXI HP0 port. And I found other bug, in some case, the few bottom results are not proper. I increase the Vertical Size, such as from 1000 to 1024, the results is OK. Any reference docs for using chipscope to moniter the axi data, I don't know how to do it, and how to read my datastream from ARM to DDR in Betaral System. In Linux, can i use the chipscope to minitor my AXI DataStream?   

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wangzhibin
Observer
Observer
5,492 Views
Registered: ‎03-19-2013

Hi, I have met another VDMA problem. When I start the vdma firstly, it works OK. But  when i execute my binary again, it comes with errors.

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