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ncalik
Visitor
Visitor
6,841 Views
Registered: ‎09-29-2010

About * operand

Hi i have a problem with * operand in vhdl. i want to multiply two bit vector but every time program gives

 

ERROR:HDLParsers:808 - "U:/FPGA_VHDL/dnm/fr.vhd" Line 15. * can not have such operands in this context.

 

i've loaded all libraries about math but cant solve it.

 

thank you


 

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.math_complex.all;
use IEEE.numeric_std.all;


entity mult is
port (
X: in std_logic_vector (7 downto 0);
Y: in std_logic_vector (7 downto 0);
P: out std_logic_vector (15 downto 0)
);


end mult;
architecture carp of mult is
begin
P <= X * Y;
end mult;

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7 Replies
eilert
Teacher
Teacher
6,838 Views
Registered: ‎08-14-2007

Hi,

the Problem you have has been solved some years ago here:

http://forums.xilinx.com/t5/General-Technical-Discussion/binary-multiplication-in-vhdl/m-p/3659

 

Besides:

Quite similare source codes, aren't they?

Is it taken  from some example in a VHDL book?

 

Have a nice synthesis

  Eilert

 

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ncalik
Visitor
Visitor
6,833 Views
Registered: ‎09-29-2010

yes i  copied codes from that page but my problem is different.

 

i want to see that error messages are not same.

 

 

thnx

 

 

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ncalik
Visitor
Visitor
6,831 Views
Registered: ‎09-29-2010

also i cant use + ,- , / oprands

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bassman59
Historian
Historian
6,807 Views
Registered: ‎02-25-2008

 


@ncalik wrote:

Hi i have a problem with * operand in vhdl. i want to multiply two bit vector but every time program gives

 

ERROR:HDLParsers:808 - "U:/FPGA_VHDL/dnm/fr.vhd" Line 15. * can not have such operands in this context.

 

i've loaded all libraries about math but cant solve it.

 

thank you


 

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.math_complex.all;
use IEEE.numeric_std.all;

 


 

 

Do NOT NOT NOT NOT use std_logic_arith. ESPECIALLY DO NOT NOT NOT use it with numeric_std.

 

 

 


 

entity mult is
port (
X: in std_logic_vector (7 downto 0);
Y: in std_logic_vector (7 downto 0);
P: out std_logic_vector (15 downto 0)
);


end mult;
architecture carp of mult is
begin
P <= X * Y;
end mult;


 

The problem is that you're trying to multiply two std_logic_vectors. std_logic_vectors do not represent numbers -- they are just vectors of bits.

 

You need to multiply numbers of type unsigned, signed, integer (with range) or natural (with range).

----------------------------Yes, I do this for a living.
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sridar
Explorer
Explorer
6,795 Views
Registered: ‎09-20-2007

Include only the following library and package and see if it helps

 

library IEEE;
use IEEE.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

FPGA freak
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bassman59
Historian
Historian
6,764 Views
Registered: ‎02-25-2008

 


@sridar wrote:

Include only the following library and package and see if it helps

 

library IEEE;
use IEEE.std_logic_1164.all;

use ieee.std_logic_unsigned.all;


 

NOOOOOOOOOOOOOOOOOOOOOOOOO!

 

Use numeric_std -- not std_logic_unsigned.

 

----------------------------Yes, I do this for a living.
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ncalik
Visitor
Visitor
6,700 Views
Registered: ‎09-29-2010

thanks to everybody for their helps

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