UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
3,716 Views
Registered: ‎04-09-2008

Absolute Voltage Limits on LVDS

I'm thinking of implementing something like this for a many (hundreds) channel ADC design I'm working on.

 

http://www.latticesemi.com/documents/WP-Creating_An_ADC_Using_FPGA_Resources.pdf?jsessionid=f030d6aaa67b2257a8fb6f2e5f60216d416b

 

It's basically a successive approximation of an analog voltage, combining a PWM with a repurposed differential input amplifier that is functioning instead as a comparator.

 

The hitch is, my voltage input can scale quite high. It would be alright for the circuit to cease functioning reliably, but destroying an FPGA I/O pin would not be an acceptable result. In other words, the failure would have to be reversible. I already have other means of detecting this failure - possibly even very quickly. But I'm worried, if that housekeeping process fails for some reason, this I/O could be subject to that voltage for a very long time.

 

My question is, what if I drive 5V into a differential amplifier that's in a bank configured with a VCCO of 3.3V (or even 1.8V)?  Will it let all the magic smoke out and stop working? Are there clamping diodes inside the I/O pin that will protect the device? What if I only have <1mA of current in this branch of the circuit? Can those diodes effectively clamp the input, without burning themselves out? What if I put a low impedance opamp driving it? I suspect the low impedance would fry it quickly.

 

Thank you.

0 Kudos
3 Replies
Scholar austin
Scholar
3,715 Views
Registered: ‎02-27-2008

Re: Absolute Voltage Limits on LVDS

p,

 

The absolute maximum ratings are in the data sheet.  At those voltages, no damage.

 

Beyond those voltages, you may, or may not damage the device.  Well beyond that, damage is almost assurred.

 

Thus, that table tells you exactly what to avoid.

 

5V on a 1.8V 7 series IO bank is almost certainly instant destruction.

 

Current shall also be less than what is specified in the data sheet:  100 mA for any sum of currents into, or out of an IO bank, less than 200 mA for the entire device.

 

So, depending on the intrinsic clamp diodes is just fine, as long as you stay within the current limits as described above.

 

Adding external clamping diodes is suggested if you feel you might even get close to the 100 mA limit.

 

Above the recommended voltages (also in the data sheet), and below the abs max -operation is not gauranteed, but there is no damage.

 

Note that driving an IO pin will power ON the IO bank (through the protecxtion diode), as an IO bank needs less than 2 mA to operate (think it is ON).  I would also look at powering ON (and OFF) to be sure you stay within any data sheet requirements for supply sequencing.

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Explorer
Explorer
3,711 Views
Registered: ‎04-09-2008

Re: Absolute Voltage Limits on LVDS

I think the external protection diode unfortunately would undermine the benefit (smaller PCB area, fewer components) of moving this circuit into the FPGA. I'm probably better off just using an external analog comparator.

 

Thanks for the reply!

 

0 Kudos
Scholar austin
Scholar
3,704 Views
Registered: ‎02-27-2008

Re: Absolute Voltage Limits on LVDS

If,

 

You can find as fast a comparator as the fully differential, rail to rail CMOS comparators already used for all the differential standards that are built into the FPGA:  Good Luck! (they don't exist).  The wiring to and from disrete comparators, and to the FPGA (for logic) is just too ugly to think about.

 

So, rather than use external diodes, what is wrong with a series resistor from the source?  If the source voltage could be as high as 5V, then limiting the total cuurent to a number of inputs in parallel to less than 100 mA implies (5-1.8)/.1=32 ohms....

 

Of course, there may be an existing A/D converter that does exactly what you want (probably there is), so not sure why you wish to do this at all?

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos