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2,587 Views
Registered: ‎04-10-2008

Add delay lower than half clock cycle

Hi everybody,

 

I would need to add some delay to an output signal, 1 or 2 ns. The signal I should delay has the same frequency that my system clock (30MHz). I do not know how to do it.

 

Thank you very much,

 

Trini

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ywu
Xilinx Employee
Xilinx Employee
2,575 Views
Registered: ‎11-28-2007

Which device? You can use phase-shift your system clock using a DCM or PLL and them use the new clock to drive the output.
Cheers,
Jim
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