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weilings
Explorer
Explorer
11,517 Views
Registered: ‎03-08-2012

Asynchronous sequential state machine

Do you have any documentation to recommend about the "Asynchronous  sequential state machine" design?

I have learnt several problems about it, but I still don't have any clue about how to design one.

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eteam00
Professor
Professor
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Registered: ‎07-21-2009

You are going to hear this sooner or later, so I'll speed up the progression:

 

Asynchronous design is NOT supported by Xilinx.  period.  Zip Zilch.  Nada.

 

You can search the forums for threads discussing asynch design, there should be plenty.  You need to know that FPGA logic elements are not conventional gates -- they are static RAM lookup tables.  This means that input signal changes which should not affect the logic element output, based on a Boolean logic table, will generate output signal glitches.  In asynch design, glitches are generally a design-killer.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
weilings
Explorer
Explorer
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Registered: ‎03-08-2012

sorry, I forgot to tell you that: in asynchronous sequential state machine design, only one input can changes at a time. This assumption is determine to bypass the glitch. 

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awillen
Mentor
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Registered: ‎11-29-2007


@weilings wrote:

sorry, I forgot to tell you that: in asynchronous sequential state machine design, only one input can changes at a time. This assumption is determine to bypass the glitch. 


You can get a glitch even with only a single input changing if you don't control the actual silicon. Which you don't when using FPGAs. A single glitch in the next-state logic will screw up your state.

 

Besides, I think the tools are unable to properly handle combinational cycles.

 

What do you want to achieve? Is this a homework assignment?



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muzaffer
Teacher
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Registered: ‎03-31-2012

I remember reading a promise from Xilinx which said if only one input changed into a LUT, the output will not glitch but I can't find it right now. It might be interesting to check it with Xilinx folks.
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weilings
Explorer
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Registered: ‎03-08-2012

I agree with you.
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weilings
Explorer
Explorer
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Registered: ‎03-08-2012

Are you sure that even if one input changes in the LUT will cause glitchs in the ouput?
And this is surely NOT a homework assignment, I just find an issue about AFSM(asynchronous finite state machine) disign when I was reviewing basic verilog knowledge, teacher won't assign a homeword this hard to us.
I just want to know how to design a AFSM in a clear way. Do you have some documentation to recommend to me? Thank you any way~
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muzaffer
Teacher
Teacher
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Registered: ‎03-31-2012

You can get a glitch even with only a single input changing if you don't control the actual silicon. Which you don't when using FPGAs. A single glitch in the next-state logic will screw up your state.

 

Gospel according to Austin says this:

 

The LUT is not glitch free.

Each bit input to the LUT slects a multiplexer path, in a binary tree.  So only a change to a single input is glitch free.  If more than one input changes, then due to the delay of each stage of the multiplexder tree, there may be glitches

 

http://forums.xilinx.com/t5/Simulation-and-Verification/Glitches-in-combinational-logic/td-p/133786

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awillen
Mentor
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Registered: ‎11-29-2007


@muzaffer wrote:

Gospel according to Austin says this:

 

The LUT is not glitch free.

Each bit input to the LUT slects a multiplexer path, in a binary tree.  So only a change to a single input is glitch free.  If more than one input changes, then due to the delay of each stage of the multiplexder tree, there may be glitches

 

http://forums.xilinx.com/t5/Simulation-and-Verification/Glitches-in-combinational-logic/td-p/133786


Interesting. But you could still get glitches, even if only a single input changes at a time, when your logic has two or more levels. Example: two LUTs A and B, the output of A is an input of B, and signal s is an input of A and B. Voilà, single input change in s results in two inputs of LUT B changing at the same time.

 

@wellings: Okay, so let's assume that your state change logic fits in a single level of LUTs. You still can't design sequential elements without precise control over the wire delays.



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eteam00
Professor
Professor
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Registered: ‎07-21-2009

Do you have any documentation to recommend about the "Asynchronous  sequential state machine" design?

 

No.  Xilinx does not support asynchronous design.  You are on your own in this endeavour.

 

I have learnt several problems about it, but I still don't have any clue about how to design one.

 

Well, then, you have quite a bit of work ahead of you.  I hope the end result is worth the time and effort you will be investing.  I would not be surprised if you must develop new design tools to help analyse and verify your designs.

 

If you are successful, you should write a book on the subject for those who wish to follow in your footsteps, as you undoubtedly will be a leader in this field.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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weilings
Explorer
Explorer
3,801 Views
Registered: ‎03-08-2012

Thank you very much for your detailed reply, and it is very helpful to me.

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lowearthorbit
Scholar
Scholar
1,018 Views
Registered: ‎09-17-2018

Aw shucks,

"Gospel according to austin" is flattering.  Thank you for your confidence in my 20 years of representing Xilinx IC designers.  Surprises me everyday to find I answered 'that' question (and tens of thousands of others).  I recommend to my colleagues, my students, to get a forum account and search here first to answer their questions.  I even look here first as I have answered so many I cannot recall them all.  You can also find the hand full of answers I got wrong and apologized for.  No one is perfect.

Now I am enjoying just being the customer.

And, yes, do not waste any time on asynchronous design.

lowearthorbit (AKA austin)