08-18-2011 10:32 PM - edited 08-18-2011 10:40 PM
How to implement Audio AGC in FPGA using VHDL?
1. Determine the algorithm you want to use. If you don't have any ideas of your own, use someone else's ideas.
2. Learn VHDL.
3. Implement the algorithm in VHDL.
4. Test and refine algorithm and implementation until design requirements are met.
Any IP cores available? Input is 16-bit,8 kHz demodulated audio.
-- Bob Elkind
08-19-2011 12:55 AM
This is not a Synthesis tool topic. You should post this message on "General Technical Discussion" board. I'll move it to that board.
08-21-2011 11:26 PM - edited 08-22-2011 10:48 AM
The suggestions I gave you were nothing more than the obvious ones. Here are some more suggestions which are also moderately obvious:
You should not expect 'portability' at the implementation level for something which is so application-specific.
Algorithms are 'portable', but not implementations.
The application-specific details (i.e. implementations) are tedious.
All of this is pretty easy to figure out. You certainly don't need me to tell you this.
This probably explains why you haven't received many offers of tried and tested code for your '16bit 8KHz' application.
The form in which you made your request suggests that you don't have much background in digital signal processing (or, more specifically, in audio processing). If this is the case, a few days spent studying the basics of the subject would be to your advantage.
To sum up: Asking for a UART core isn't a big deal -- the application is pretty uniform, and the effort to customise the module to your application is minimal. DRC implementation is more complicated than UARTs. It must be customised to your application, and customisation requires an understanding of the design principles involved.
-- Bob Elkind
02-26-2012 02:24 AM
Hi bob. Now a days I am trying to implement something in my fpga to control the maximum value for 75KHz deviation in FM modulation and If the value of signal is above 75KHz the reduce the whole signal so it doesn`t exceed 75Khz deviation ( I don`t know which technique is good and I google it and found dynamic range control and in IP forum someone said AGC is fine) When I saw your comment here, you said: Most audio dynamic range compression (DRC) circuits are in ASICs and DSPs, not FPGAs. What do you mean? Do you mean DRC is not a good solution for implementing in FPGA for audio process and controlling deviation of FM? How about AGC? Or if you have any other solution please let me know.
I am good enough in Signal processing and I have done all my project. But I need to control the deviation and now I am freeze. I confused and I need some useful help. I really appreciate if you help me.
02-26-2012 07:54 AM
Please start a new thread. In your new thread, suggest you post a block diagram which describes your intended design.
-- Bob Elkind