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Contributor
Contributor
965 Views
Registered: ‎11-28-2018

Auto-generation of AXI4 register blocks

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Imagine you want to generate an AXI4 register block automatically from some sort of register definition file. It might be IP-XACT or it might be some other bespoke format.

What (free) tools would you use for this?

 

What I have done so far in my current company is start from a boilerplate AXI4 register block in Verilog generated by Vivado and then hack it to suit my needs. In a previous company we used to have a nice custom tool that built arbitrary register blocks from bespoke XML definitions. This is the kind of tool I'm looking for and I suspect there must something like this out there, even if I could not find it.

 

Any suggestions? What do you use yourselves in a case like this?

 

Thanks!

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Moderator
Moderator
867 Views
Registered: ‎11-09-2015

Hi jaruiz@kaleao,

I do not think Xilinx has a solution for this.

You can always contact the author of the AirHDL. He might sell it solution this way you could have it.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
888 Views
Registered: ‎11-09-2015

Hi jaruiz@kaleao,

I think https://airhdl.com/index.jsp might be a good ressource for you. I never tried it but it seems to be what you are looking for.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Contributor
Contributor
873 Views
Registered: ‎11-28-2018

Thank you, I was aware of that web. But it seems to be an online-only tool?

Does it not bother you that it may disappear or change at any time? How will you support your project in a few years' time?

 

They do have a command line tool you can download and use locally, but it is not free so I cannot tweak it. And I will want to tweak it.



I suspect a lot of people has rolled their own register generation tool and I hoped someone would have made theirs available...

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Highlighted
Moderator
Moderator
868 Views
Registered: ‎11-09-2015

Hi jaruiz@kaleao,

I do not think Xilinx has a solution for this.

You can always contact the author of the AirHDL. He might sell it solution this way you could have it.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Scholar
Scholar
724 Views
Registered: ‎05-21-2015

jaruiz@kaleao,

There is an open source solution with a similar capability that I have written and maintain.  It is called AutoFPGA.  It can be used to automatically add peripherals to a bus interconnect based upon the configuration files given to it at a command line.

At present, it only supports Wishbone.  It does not support AXI or even AXI-lite. These are on my to-do list, but I really don't have any projects currently requiring them so they might take some time before they get implemented.

Feel free to contact me if you'd like to discuss this further.

Dan