03-29-2015 11:54 PM
I am using axi_bram_Cntrlr for one of my project. i connected the single port of axi bram Controller to Native single port Block RAM inside ISE, Another port of axi Controller is left open.
When i use the funtion xil_WriteReg, xil_ReadReg funtion for write and read, it is not able to perform the read write function.
Can Anybody give the solution for the same...
Is it necessary to connect the controller to axi_bram memory ony??...or any other issues in clocking and reset..
03-30-2015 10:16 PM
In .MHS file you cant see the connections..since PORT A is connected to External Ports, I used Native Block RAM in ISE,
i decoded WEN from contrller as
BRAM_WE <= "1" when (cntrlr_WEN = "1111") else "0";
Bram_Din <= cntrlr_Dout
Bram_Dout <= cntrlr_Din
Bram_EN <= '1';
Bram_Clk <= cntrlr_CLK
PORTB of axi_cntrlr left open
It is still not accesing the memry inside ISE