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6,950 Views
Registered: ‎04-01-2013

Axi bram controller Microblaze

Hi,

     I am using axi_bram_Cntrlr for one of my project. i connected the single port of  axi bram Controller to Native single port Block RAM inside ISE, Another port of axi Controller is left open.

 

When i use the funtion xil_WriteReg, xil_ReadReg funtion for write and read, it is not able to perform the read write function.

 

 

Can Anybody give the solution for the same...

 

Is it necessary to connect the controller to axi_bram memory ony??...or any other issues in clocking and reset..

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Xilinx Employee
Xilinx Employee
6,926 Views
Registered: ‎06-14-2012

Re: Axi bram controller Microblaze

How is the connection of AXI BRAM controller? Please share the mhs if you can.

 

Regards

Sikta

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6,916 Views
Registered: ‎04-01-2013

Re: Axi bram controller Microblaze

In .MHS file you cant see the connections..since PORT A is connected to External Ports, I used Native Block RAM in ISE,

 

i decoded WEN from contrller as 

 

BRAM_WE <= "1" when (cntrlr_WEN  = "1111") else "0";

 

Bram_Din <=  cntrlr_Dout

Bram_Dout <= cntrlr_Din

Bram_EN <= '1';

Bram_Clk <= cntrlr_CLK

 

PORTB of axi_cntrlr left open

 

It is still not accesing the memry inside ISE

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