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ftamulonis
Visitor
Visitor
4,624 Views
Registered: ‎10-22-2013

BRAM_TDP_MACRO warnings

Hi Everyone,

 

I am using a spartan 6 on the SP605 development board. On the FPGA I am running the TEMAC 5.2 IP CORE with some modifications so that data that flows through the MAC comes from the FMC-LPC connector. The data that I am assigning is coming in as a vector (7 downto 0) :

 

deswbo_data: in std_logic_vector(7 downto 0);

 

in order for this data to be assigned in the program I am using the included pattern generator (I have commented the parts that I do not want out) : 

----------------------------------------------------------------------------------------------------------

-- now generate the TDATA output

data_p : process (axi_tclk)
begin
if axi_tclk'event and axi_tclk = '1' then
if enable_pat_gen = '1' then
--if gen_state = HEADER and (tready = '1' or tvalid_int = '0') then
tdata <= deswbo_data; --lut_data;  ----------------------------------------------------THIS IS WHERE I ASSIGN THE INCOMING DATA
--elsif gen_state = SIZE and tready = '1' then
-- if header_count(3) = '1' then
-- tdata <= "00000" & std_logic_vector(pkt_size(10 downto 8));
-- else
-- tdata <= std_logic_vector(pkt_size(7 downto 0));
-- end if;
else --tready = '1' then
--tdata <= std_logic_vector(byte_count(7 downto 0));
-- end if;
end if;
else

end if;
end process data_p;

-------------------------------------------------------------------------------------------------------------------------

this process assigns tdata when the pattern generator is enabled if I dont have it enabled I do not want it to do anything. 

 

After this process and becomeing antoher signal (tx_axis_fifo_tdata) it completes its journey by storing the data in a BRAM :

 

 

ramgen_l : BRAM_TDP_MACRO
generic map (
DEVICE => "SPARTAN6",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9,
READ_WIDTH_A => 9,
READ_WIDTH_B => 9)
port map (
DOA => rd_bram_l_unused,
DOB => rd_eof_data_bram_l,
ADDRA => wr_addr_slv,
ADDRB => rd_addr_slv,
CLKA => tx_fifo_aclk,
CLKB => tx_mac_aclk,
DIA => wr_eof_data_bram, ------------------------------------------This should be where the data is stored 
DIB => GND_BUS(8 downto 0),
ENA => VCC,
ENB => rd_en,
REGCEA => VCC,
REGCEB => VCC,
RSTA => tx_fifo_reset,
RSTB => tx_mac_reset,
WEA => wr_en_l_bram,
WEB => GND

So when I sythensize this design I get two warnings that make me question the design:

 

HDLCompiler:321 - "N:/O.76xd/rtf/devlib/vhdl/src/unimacro/BRAM_TDP_MACRO.vhd" Line 1236: Comparison between arrays of unequal length always returns FALSE.

 

and 

 

HDLCompiler:634 - "N:/O.76xd/rtf/devlib/vhdl/src/unimacro/BRAM_TDP_MACRO.vhd" Line 1029: Net <dia_pattern[31]> does not have a driver.

 

Right now when I run the program nothing pops up on Wireshark. 

Any thoughts on this would be great  and Thank you in advance. I have attached the .xco file for your convence. 

 

 

 

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4 Replies
vemulad
Xilinx Employee
Xilinx Employee
4,605 Views
Registered: ‎09-20-2012

Hi,

 

Did you check the below threads

http://forums.xilinx.com/t5/Synthesis/BRAM-SDP-MACRO-xst-warnings/td-p/204869 

http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan-6-BRAM-instantiation/td-p/133384 

 

Thanks,

Deepika.

Thanks,
Deepika.
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ftamulonis
Visitor
Visitor
4,601 Views
Registered: ‎10-22-2013

Hi Deepika,

 

Thank you for those posts. I did check them out. The first I read through and while providing some good information did not provide specific information for my problem and that post did not have an accepted answer. The second link sent me to a page that says it has Invalid Parameters Specified or the page could not be found. 

 

 

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ftamulonis
Visitor
Visitor
4,589 Views
Registered: ‎10-22-2013

So now I am trying somthing different. In the top Level module

 

I have the following process:

 

dataflow_p:process(tx_mac_aclk)
begin
if tx_mac_aclk'event and tx_mac_aclk ='1' then
if tx_reset = '1' then
tx_axis_fifo_tdata <= X"01";
else
tx_axis_fifo_tdata <= deswbo_data;
end if;
end if;
end process;

 

while this synthesizes properly its does not translate and I get the following erorrs:

 

ERROR:ConstraintSystem:58 - Constraint <INST
"*user_side_FIFO/tx_fifo_i/rd_addr_txfer*" TNM =
"tx_fifo_rd_to_wr";>
[C:/Users/ftamulon/Desktop/FivePointTwoEthernetCVS/ipcore_dir/tri_mode_eth_ma
c_v5_2/example_design/tri_mode_eth_mac_v5_2_example_design.ucf(217)]: INST
"*user_side_FIFO/tx_fifo_i/rd_addr_txfer*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST
"*user_side_FIFO/tx_fifo_i/rd_col_window_pipe_1" TNM =
"tx_fifo_rd_to_wr";>
[C:/Users/ftamulon/Desktop/FivePointTwoEthernetCVS/ipcore_dir/tri_mode_eth_ma
c_v5_2/example_design/tri_mode_eth_mac_v5_2_example_design.ucf(220)]: INST
"*user_side_FIFO/tx_fifo_i/rd_col_window_pipe_1" does not match any design
objects.
ERROR:ConstraintSystem:58 - Constraint <INST
"*user_side_FIFO/tx_fifo_i/wr_col_window_pipe_0" TNM =
"tx_metastable";>
[C:/Users/ftamulon/Desktop/FivePointTwoEthernetCVS/ipcore_dir/tri_mode_eth_ma
c_v5_2/example_design/tri_mode_eth_mac_v5_2_example_design.ucf(228)]: INST
"*user_side_FIFO/tx_fifo_i/wr_col_window_pipe_0" does not match any design
objects.
ERROR:ConstraintSystem:58 - Constraint <INST
"*user_side_FIFO/tx_fifo_i/rd_addr_txfer*" TNM =
"tx_addr_rd";>
[C:/Users/ftamulon/Desktop/FivePointTwoEthernetCVS/ipcore_dir/tri_mode_eth_ma
c_v5_2/example_design/tri_mode_eth_mac_v5_2_example_design.ucf(233)]: INST
"*user_side_FIFO/tx_fifo_i/rd_addr_txfer*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST
"*user_side_FIFO/tx_fifo_i/wr_rd_addr*" TNM =
"tx_addr_wr";>
[C:/Users/ftamulon/Desktop/FivePointTwoEthernetCVS/ipcore_dir/tri_mode_eth_ma
c_v5_2/example_design/tri_mode_eth_mac_v5_2_example_design.ucf(234)]: INST
"*user_side_FIFO/tx_fifo_i/wr_rd_addr*" does not match any design objects.

 

 

Why would these errors pop up if the only thing I added was a process that runs off the correct clock ?

 

 

Again thak you in advance

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vemulad
Xilinx Employee
Xilinx Employee
4,577 Views
Registered: ‎09-20-2012

Hi,

Regarding the new error, it is good if you can create a new thread.

It looks like the hierarchical name of the instances mentioned in ucf constraints have been changed or it can be that these instances does not exist. Open technology schematic and search for these instances. Give the complete name of instances as seen in technology schematic (or part of name preceded by * wildcard) in the ucf and rerun implementation.

Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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