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Posts: 14
Registered: ‎07-14-2017

BUFGMUX udefined output

Hello all,


I am struggling to understand how exactly do BUFGMUX's function. In fact, my design consists of BUFGCTRL (having the CE pin as select line, exactly like pg 43 at this document  https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

 The document also states that if you use CE as select then if you violate the setup/hold times you are  vulenrable to runt pulses, glitches and all sort of unwanted behavior. In the timing simulation i performed though, I am seeing this



CE is the select line which chooses to switch to I1 from I0.

I0 , I1 are the available clocks to select from

O is the BUFGMUX output.


What troubles me is that even if the CE signal does not seem to violate any setup/hold time (It is way far from the rising edge of both I0 and I1 pulses) it produces an undefined signal.

Is there anyone having experienced the same behavior. Does anybody knows exactly the conditions that should be met to avoid the specific behavior?


Thanks a lot in advance.



Xilinx Employee
Posts: 559
Registered: ‎10-11-2007

Re: BUFGMUX udefined output

How exactly do you know you are NOT violating the CE setup/hold when it's not checked?  Use the S pins if are are concerned about a clock glitch. 

Posts: 5,141
Registered: ‎03-31-2012

Re: BUFGMUX udefined output

@vatistas did you really measure CEx to Ix delays and make sure they pass timing? Also watch the console output for any timing violation reporting. Finally I am not sure if only posedge Ix counts. Check if you need to stay away from both edges.

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Posts: 14
Registered: ‎07-14-2017

Re: BUFGMUX udefined output

Yes I did measure the time difference from both edges and they do not violate any setup or hold time as they are reported on the Virtex-7 familly datasheet. After some more simulations I have narrowed down the problem in the following scenario. The BUFGMUX (with CE as select pin) produces a metastable output when you give 2 changes back to back (i.e CE = "0" and then CE="1") before the BUFGMUX even manages to output a pulse. Probably there is some weird thing going on with the FFs and the signals inside the BUFGMUX but since it I cannot see inside the primitive I am not sure. This limitation though (mtastability) prohibits me from being able to correctly change my clock with a 1 clock cycle granularity and the Xilinx User guide doesnt mention that specific behavior.