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me.arunkumars
Visitor
Visitor
3,516 Views
Registered: ‎10-03-2011

Behavior of ~

Hi 

 

I just wanted to know if the below problem is compiler specific or the standard defines it as such.

 

Suppose the code is 

 

module test(

    input clk,

    input en_bar,

    output reg [4:0] count

    );

 

   always @(posedge clk)

              count<=count + ~en_bar;

endmodule

 

I expected it to work as 

--        count<= count + 1'b1; // when en_bar is 0

--        count<= count + 1'b0; // when en_bar is 1

 

But in Xilinx it behaves as 

--        count<= count + {5'b{1'b1}}; //when en_bar_is 0

 

i.e. the synthesis tool first appends required zeros and then does bitwise not.

 

Yeah the work around is 

           count<= count + !en_bar;// instead of ~en_bar

 

But wouldn't it be better if ~ behaviour is changed

 



 

 

 

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gszakacs
Instructor
Instructor
3,515 Views
Registered: ‎08-14-2007

You may want to post your question on comp.lang.verilog, but I believe that

the XST behavior does follow the Verilog language reference manual.  i.e.

the RHS arguments are first extended as necessary to meet the LHS size requirements

and then operations are performed.  So en_bar is first zero-extended to 5 bits

and then bitwise inverted.  To be more clear on this sort of usage you can

break up the function with an additional wire:

 

wire en_true;

assign en_true = ~en_bar; // This will be single-bit 0 or 1

 

then use

 

  count <= count + en_true;  // This will add 0 or 1

 

-- Gabor

-- Gabor
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bassman59
Historian
Historian
3,512 Views
Registered: ‎02-25-2008


@gszakacs wrote:

You may want to post your question on comp.lang.verilog, but I believe that

the XST behavior does follow the Verilog language reference manual.  i.e.

the RHS arguments are first extended as necessary to meet the LHS size requirements

and then operations are performed.  So en_bar is first zero-extended to 5 bits

and then bitwise inverted.  To be more clear on this sort of usage you can

break up the function with an additional wire:

 

wire en_true;

assign en_true = ~en_bar; // This will be single-bit 0 or 1

 

then use

 

  count <= count + en_true;  // This will add 0 or 1

 

-- Gabor


This is one reason why I hate Verilog.

----------------------------Yes, I do this for a living.
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