UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer fab
Observer
252 Views
Registered: ‎04-09-2018

Bending stress on FPGA

Jump to solution

Dear all,

I would ask you about the acceptable level of bending stress at which a FPGA can be put. The specific case is:

I have a custom board with a Kintex Ultrascale mounted; the pcb "naked" (without any component soldered) is bended but the bending value is inside the acceptable parameter of 0,075 (if I remember the maximum value correctly) if it didn't go through the thermal cycle for the component soldering, if it goes through it the bending is outside the acceptable value of 0,075 ; the shape of the card is a rectangular with the ratio between the sides similar to 2,5 square attached in series (sort of). The previous description was only to visualize the situation. The problem is that the pcb "naked" that went through the thermal cycle has the shape of a curve (outside the acceptable parameter 0,075), but the pcb with the component mounted that went through the thermal cycle is curve+straight+curve because the FPGA is keeping the middle curve straight with its rigidity.

I'm searching a manual that tells me which is the range or maximum value of this type of stress on a FPGA (Kintex Ultrascale in this specific case) that I tried to explain to you. I checked the manuals ug583, ug1099 but I didn't find what I was searching. Maybe the manuals are the correct ones but I didn't know what parameter search. Anyway I hope to be enough complete in my description. Thank you for your attention.

Fab

0 Kudos
1 Solution

Accepted Solutions
Scholar drjohnsmith
Scholar
223 Views
Registered: ‎07-09-2009

Re: Bending stress on FPGA

Jump to solution
The exampke I have had of bending stress on an fpga
it was not the fpga that was the limit, but how hard t was soldered down,
the pads under the balls peeled off of the pcb first, the fpga was fine.

and thats something Xilinx can't control,

Peel strength we also found was variable depending upon process as well as the type of board material.
0 Kudos
1 Reply
Scholar drjohnsmith
Scholar
224 Views
Registered: ‎07-09-2009

Re: Bending stress on FPGA

Jump to solution
The exampke I have had of bending stress on an fpga
it was not the fpga that was the limit, but how hard t was soldered down,
the pads under the balls peeled off of the pcb first, the fpga was fine.

and thats something Xilinx can't control,

Peel strength we also found was variable depending upon process as well as the type of board material.
0 Kudos