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robinbarlis

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05-30-2013 01:35 AM

2,664 Views

Registered:
05-30-2013

Binary Divider Warnings

Hi! I am working on a verilog code which works as a binary divider. This is my code so far:

module div1(

input clk, res, start,

input [11:0] dividend, divisor,

output reg[11:0] quotient,

output reg stop,

output[12:0] dumyout,

output[6:0] dumyout2,

output[4:0] dumyout3

);

//reg[11:0] quotient1;

reg [11:0] q3;

reg [31:0] q4;

reg [11:0] q2, q11, q12;

reg [2:0] cntr;

reg [3:0] cntr2;

reg [3:0] cntra, cntrb, a, b;

reg [12:0] q1;

always@(posedge clk or posedge res)

begin

if (res)

begin

// q3 is the temporary quotient

q11 <= 12'b111111111111;

q12 <= 12'b111111111111;

q1 <= 13'b1111111111111;

q2 <= 12'b111111111111;

q3 <= 12'b111111111111;

q4 <= 32'b11111111111111111111111111111111;

cntr <= 3'b000;

cntr2 <= 4'b1011;

// cntr3 <= 8;

stop <= 1'b1;

cntra <= 4'b1111;

cntrb <= 4'b1111;

a<= 4'b1111;

b<= 4'b1111;

quotient<=12'b111111111111;

end

else

begin

case (cntr)

000: begin stop <= 1'b0;

if (start == 1'b1)

begin

q2 <= divisor;

q11 <= dividend;

q12 <= divisor;

q1 <={1'b0,dividend} ;

cntr <= 3'b001;

cntra <= 4'b0000;

cntrb <= 4'b0000;

a<= 4'b0000;

b<= 4'b0000;

quotient <= 12'b000000000000;

q3 <= 12'b000000000000;

q4 <= 32'b00000000000000000000000000000000;

stop <= 1'b0; end end

001: begin

if ( (q11 == q12) || (q11 == 12'b000000000000) )

begin cntr <= 3'b111; end

else

begin

if (q1[11] == 1'b0)

begin q1 <= q1 << 4'b0001;

cntra <= cntra + 4'b0001; end

if (q2[11] == 1'b0)

begin q2 <= q2 << 4'b0001;

cntrb <= cntrb + 4'b0001; end

if ( (q1[11]==1'b1) && (q2[11] ==1'b1) )

begin cntr <= 3'b010; end

end end

010: begin

a <= (cntrb - cntra) + 4'b0001;

b <= (cntra -cntrb) - 4'b0001;

cntr <= 3'b011; end

011: begin

if (q1[12:0] >= {1'b0,q2} )

begin q1 <= q1 - q2;

q1 <= q1 << 4'b0001;

q1[0] <= 1'b0;

q3[cntr2] <= 1'b1; end

else

begin q3[cntr2] <= 1'b0;

q1 <= q1 << 4'b0001; end

if (cntr2 == 4'b0000)

begin cntr <= 3'b100; end

else

begin cntr2 <= cntr2 - 4'b0001; end

//cntr3 <= cntr3 -1;

end

100: begin

cntr2 <= 11;

stop <= 1'b0;

q4[20:9] <= q3;

cntr <= 3'b101;

end

101: begin

if (b == 4'b1111)

begin q4 <= q4 << 4'b0001; end

if ((q11 > q12) && (a>0) )

begin q4 <= q4 << a; end

if ((q11 < q12) && (b >0) )

begin q4 <= q4 << b; end

cntr <= 3'b110;

end

110: begin //if q11 > q12 then

quotient <= q4[24:13];

stop <= 1'b1;

cntr <= 3'b000;

end

//elsif q11 < q12 then

// quotient <= q4(47 downto 0);

111: begin

if (q11 == 12'b000100000000)

begin quotient <= 12'b000000000000; end

else

begin quotient <= 12'b000100000000; end

stop <= 1'b1;

cntr <= 3'b000;

end

default: begin quotient <= q4[24:13];

q1<=13'b1111111111111;

q3 <= 12'b111111111111;

a<= 4'b1111;

b<= 4'b1111;

end

endcase

end

end

//assign quotient = quotient1;

assign dumyout = q4[12:0];

assign dumyout2= q4[31:25];

assign dumyout3= a+b;

endmodule

When I synthesized this code the following warnings came up:

WARNING:Xst:646 - Signal <q3> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

WARNING:Xst:646 - Signal <q1<12>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

WARNING:Xst:646 - Signal <cntr2> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Register <b> equivalent to <a> has been removed

Register <q4<10>> equivalent to <q4<0>> has been removed

Register <q4<11>> equivalent to <q4<0>> has been removed

Register <q4<12>> equivalent to <q4<0>> has been removed

Register <q4<13>> equivalent to <q4<0>> has been removed

Register <q4<14>> equivalent to <q4<0>> has been removed

Register <q4<15>> equivalent to <q4<0>> has been removed

Register <q4<16>> equivalent to <q4<0>> has been removed

Register <q4<17>> equivalent to <q4<0>> has been removed

Register <q4<18>> equivalent to <q4<0>> has been removed

Register <q4<19>> equivalent to <q4<0>> has been removed

Register <q4<1>> equivalent to <q4<0>> has been removed

Register <q4<20>> equivalent to <q4<0>> has been removed

Register <q4<21>> equivalent to <q4<0>> has been removed

Register <q4<22>> equivalent to <q4<0>> has been removed

Register <q4<23>> equivalent to <q4<0>> has been removed

Register <q4<24>> equivalent to <q4<0>> has been removed

Register <q4<25>> equivalent to <q4<0>> has been removed

Register <q4<26>> equivalent to <q4<0>> has been removed

Register <q4<27>> equivalent to <q4<0>> has been removed

Register <q4<28>> equivalent to <q4<0>> has been removed

Register <q4<29>> equivalent to <q4<0>> has been removed

Register <q4<2>> equivalent to <q4<0>> has been removed

Register <q4<30>> equivalent to <q4<0>> has been removed

Register <q4<31>> equivalent to <q4<0>> has been removed

Register <q4<3>> equivalent to <q4<0>> has been removed

Register <q4<4>> equivalent to <q4<0>> has been removed

Register <q4<5>> equivalent to <q4<0>> has been removed

Register <q4<6>> equivalent to <q4<0>> has been removed

Register <q4<7>> equivalent to <q4<0>> has been removed

Register <q4<8>> equivalent to <q4<0>> has been removed

Register <q4<9>> equivalent to <q4<0>> has been removed

I also tried simulating but the quotient output was incorrect.

I am quite new to Verilog, so i'm having a hard time trying to troubleshoot the problem. I will appreciate your concerns and suggestions

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bassman59

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05-30-2013 09:50 AM

2,648 Views

Registered:
02-25-2008

Formatting and comments help.

----------------------------Yes, I do this for a living.

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