01-05-2010 10:09 AM
Is it possible to have a CPLD (ie spartan 2) communicate with a power supply and use that supply for its power source.?
I want to let the HDL routine change voltage levels and so forth for active power management.
(ie: have an ALU implemented on the CPLD, and when math operands are performing ramp up the voltage as needed, and then when they are done to return to nominal (standby) levels.
would this be feasible?
01-05-2010 11:37 AM
Spartan 2 is not a CPLD, it is a FPGA device.
Having the FPGA tell a power supply what voltage it would like to operater at is fine, as long as the power supply stays within the recommended limits for that supply (from the data sheet).
Operation outside of this recommnended range means that whatever happens, happens, and whatever you get, you get (don't call or ask us, as if it isn't in the recommended range, we have nothing to say).
01-05-2010 12:16 PM
want to have some sort of power management, do I need to have a constant voltage from the power supply ------> spartan 2.
I would like to alter the supply to the Spartan 2 as needed, such as drive the voltage down when its not doing anything and ramp it up when its performing calculations.
would a Finite State Machine help me implement this?
01-05-2010 02:06 PM
The Spartan-II family supports a VCCINT of 2.5V +/- 5% (+/- 125mV) for correct operation.
Exceeding the voltage could damage the device.
Dropping the voltage down too far (below 1.6V) will cause the device configuration memory cells to lose data and reinitiate the configuration sequence.
01-05-2010 02:09 PM
I see, so I need to have a min voltage of ca 1.6v running it.
would I be correct in assuming that an ALU block would use up more power, ? i would like to find out a way to increase the voltage for this particular operation, and then reduce it back to 1.6v.
01-05-2010 02:26 PM
Operation of the device outside of the 2.5V +/- 5% range is not guaranteed.
01-05-2010 02:42 PM
so I would be able to use a hdl routine to alter voltages of a VRM module, but using a routine to alter voltage within the FPGA itself is not (totally)feasible?
01-05-2010 02:52 PM
Would this mean that to implement my design or idea that I would need to associated the ALU behaviour (power management bllock) outside of the actual FPGA itself (since it needs a constant supply..)
something like this
I would use a hdl routine to control/monitor the VRM voltage according to the load requirements.
01-06-2010 01:31 PM
the operating limits of the spartan 2 are 1.4 > 3.6 for Vcco
if I keep within these limits would it be possible to ramp up the Vcoo for ALU operands and ramp it down for zero activity?
I am not keen on using clocking to reduce power as I am not interested in reducing the power inside the FPGA, moreso communicating with a power source for power management.
01-06-2010 03:25 PM
You can not reduce the voltage below the Vmin limit in the data sheet and expect anything whatsoever to happen in a predictable way.
The recommended range is 2.5v, +/- 125 mV (+/-5%).
If you reduce the voltage lower than this, you are operating outside of the data sheet recommended specifications, and you may have fun, and learn something, but Xilinx has nothing to say about using our chips in unspecified ways,
01-06-2010 04:08 PM
Thanks for youe reply.
If i were to use a spartan 3 dev kit, could I use an external module and use this module for my power management (and keep a steady Vccint to the FPGA.)
The ext module could implement an ALU/Counter or something like that which I could ramp up and down its supply voltage according to its activity.?
01-07-2010 08:06 AM
I do not understand what you wish to do. You need to power the FPGA within its recommended operating levels.
If you want to use the FPGA to implement a power controller, to control something else, that sounds fine, but I don't see why you would be asking this: why ask "may I use the FPGA to control something else?" It is a silly question.
It is liking asking, "I want to use the FPGA to do something useful." Of course!
The FPGA is not a piece of jewelry, it is not a coffee cup coaster: it is a field programmable gate array: use it to do somethign useful!
But, use it within the recommended specifications as outlined in the data sheet, and for purposes consistent with its intended use.