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Adventurer
Adventurer
5,261 Views
Registered: ‎03-27-2013

Cache Memory for Custom Logic

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How can I implement a cache memory for look-up purposes which works with my custom logic, not Microblaze or PPC or ARM?

I have implemented different cache architectures using VHDL or Verilog, pipelined them, worken on performance, but they cannot afford my performance requirements. On the other hand Microblaze has cache option. This means that there should be a way which implements an efficient cache memory. If there was a cache IP like SDRAM or DRAM, etc it would be nice; nonetheless it seems there is no such option.

 

How could I instance a cache memory using Xilinx/FPGA features which communicates with my custom logic?

Please keep in mind that there is no Microblaze or PPC or ARM processor.

Currently I'm using Spartan-6 platform, but if there is any way to implement cache in an FPGA using ISE/FPGA features in any of families, please inform me.

 

Thanks

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Explorer
Explorer
6,746 Views
Registered: ‎05-12-2011

Re: Cache Memory for Custom Logic

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Perhaps content addressable memory would suit your needs?  Check out xapp1151 Parameterizable Content-Addressable Memory.

 

Cheers,

-Doug

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Mentor hgleamon1
Mentor
5,253 Views
Registered: ‎11-14-2011

Re: Cache Memory for Custom Logic

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I'm not really clear on what you are trying to do. Are the BRAM resources in the FPGA not suitable?

 

What are your performance requirements? How much data? What size of RAM?

 

Regards,

 

Howard

 

----------
"That which we must learn to do, we learn by doing." - Aristotle
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Explorer
Explorer
6,747 Views
Registered: ‎05-12-2011

Re: Cache Memory for Custom Logic

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Perhaps content addressable memory would suit your needs?  Check out xapp1151 Parameterizable Content-Addressable Memory.

 

Cheers,

-Doug

View solution in original post

Adventurer
Adventurer
5,242 Views
Registered: ‎03-27-2013

Re: Cache Memory for Custom Logic

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Dear hgleamon1,

Thanks for your reply.

BRAM resources are sequential RAMs. You can address only one entry of RAM each clock cycle. If you have a large lookup table it would take much time to search and find necessary data.

On the other hand, a cache or CAM can be searched in one clock cycle. So BRAMs in the FPGA are not suitable.

I need a 1 clock cycle read operation. Cache should be at least of size 64x54 bits (64 entries, each 54 bits). Clock frequency must be at least 130 MHz running on Spartan-6.

 

Dear dchavir,

Thanks for your advice. CAM is the same cache, and its exactly what I need. xapp1151 was a very helpful reference. I should test it to see if it matches my performance requirements.

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Historian
Historian
5,233 Views
Registered: ‎01-23-2009

Re: Cache Memory for Custom Logic

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Just a point of clarification - a cache is not the same as a CAM. What you are looking for is clearly a CAM, which is a Content Addressable Memory - you present the data to the CAM and it says "yes, its in here at address X" or "no its not here".

 

A cache is a mechanism for intelligently moving data from a slow memory to a faster memory on an as-needed basis. The main memory is big and slow (i.e. DRAM) - the cache is much smaller and faster (i.e. SRAM). There is therefore a many-to-one mapping between where a piece of data lives in the main memory and cache memory. In a direct mapped cache, the data is simply stored at the same location as the lower bits of the main memory - i.e. the more significant address bits (lets say M) are discarded. Thus, of all the 2^M main memory addresses that have the same lower bits, only one can be in the cache at the same time. Cache is also usually done on a page basis - the smallest unit of data transferred from main memory to cache (the page size) is relatively bit - like 128 bytes.

 

In a set associative cache, each lower address group has a number of entries - in a 4-way set associative cache there are 4 locations available for the same lower addresses. Within the group of 4, any of the 2^M locations can be stored. To figure out if one of the 2^M is in the cache, all 4 entries must be compared against the upper M address bits of the 4 lines currently in the cache. There are lots of implementations, but the comparison of the M upper bits in the 4 locations is basically a four entry CAM (although its usually just done with a wide SRAM).

 

Avrum

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Adventurer
Adventurer
5,222 Views
Registered: ‎03-27-2013

Re: Cache Memory for Custom Logic

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Dear avrumw

Thanks for your point.

You are right, I just called it cache because content addressable feature of cache was more present in my mind. CAM is not exactly the same as cache, as you mentioned.

If you have any comments on CAM implementation on Spartan-6 (or any other) let me know please.

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