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lank20125
Newbie
Newbie
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Registered: ‎02-21-2014

Camera link transmitter using SelectIO IP

The selectIO wizard says that it can be configured as a camera link transmitter. After configuring it in this mode, I have clk_in and clk_div_in as clock inputs and clk_out_to_pins (differential signal) as clock output. The documentation on this block isn't clear, but I am providing my pixel clock (40 MHz) on clk_div_in and a 7x clock on clk_in. The data seems to get serialized properly, but the 7x clock gets put out on the clk_out_to_pins. My understanding is that camera link wants the pixel clock on the bus not the fast clock. I don't see anything in the IP setup to change this. Am I missing something? Is there an issue with the IP block? I'm using Vivado 2013.4 and version 5.1 of the SelectIO block.
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17 Replies
gszakacs
Instructor
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Registered: ‎08-14-2007

Can't comment on the IP generated by the Select IO wizard, but Camera Link data is sent using the Channel-Link protocol which is described in the data sheets for the National (now TI) DS90CR287 and DS90CR288A.  The clock on the link looks like a data pattern with 3 high and 4 low bits if I recall correctly.  something like "0011100" and aligned with the data.  This clock should be created using an OSERDES just like the other data lines.  So it's not really just the input pixel clock, but it runs at the pixel clock rate.

 

[Edit] Got that backwards:

 

should be 4 high and 3 low making the equivalent data pattern "1100011" as aligned with the 7-bit data.  The data sheet is here, see page 9.

-- Gabor
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sunnow
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Registered: ‎07-24-2008

Encounter same issue with you. I guess uncheck ' Enable forward clock ' item in the wizard.And then generate 4:3 duty clock by yourself,its speed should be same as pixel clock. But I am confused how to generate this special clock. By the way,how do you map your data queue for base configuration?

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bassman59
Historian
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Registered: ‎02-25-2008


@sunnow wrote:

Encounter same issue with you. I guess uncheck ' Enable forward clock ' item in the wizard.And then generate 4:3 duty clock by yourself,its speed should be same as pixel clock. But I am confused how to generate this special clock. 


I generate the Camera Link pixel clock output using a small LUT-based ROM. This "clock' channel looks exactly like the four data serializer channels, except that its source is the ROM instead of actual pixel data.

----------------------------Yes, I do this for a living.
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sunnow
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Registered: ‎07-24-2008

Hi bassman59, could you explain clearly how to generate the clock with you method LUT-based ROM? And this clock can be synchronous to pixel clock,otherwise serializer will be error?

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jenslin
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Registered: ‎12-13-2010

I modified the clock forwarding OSERDES block inside the generated code from the SelectIO wizard to put out the 1100011 bit pattern.  Just as the data gets serialized with this block, you can generate a 4/3 clock this way.

 

I've got to think that the clock fowarding piece of the SelectIO IP for cameralink is a bug.

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sunnow
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Registered: ‎07-24-2008

Actually I have tried you method.But data and clcok both use OSERDES block, ISE will report error that 'no placeable site' in half bank.

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bassman59
Historian
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Registered: ‎02-25-2008


@sunnow wrote:

Hi bassman59, could you explain clearly how to generate the clock with you method LUT-based ROM? And this clock can be synchronous to pixel clock,otherwise serializer will be error?


Depends on how you serialize your data.

----------------------------Yes, I do this for a living.
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yandash
Visitor
Visitor
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Registered: ‎12-05-2013

I also encountered the same issue and resolved it by driving 1100011 pattern through another OSERDES and have seen it work in hardware. I also opened a webcase on that in XILINX trying to understand why do they call their IP "Camera Link Transmitter" as this IP has nothing to do with Camera link apart from the fact it has 4 LVDS lanes with 1:7 serialization factor. Unfortunately, the XILINX support engineer seemed not familiar with Camera link so he did not understand what I was talking about...

Summary - generate the clock (and the camera link bits mixing as well) by yourself since XILINX do not really provide you Camera Link Transmitter IP.....

jenslin
Visitor
Visitor
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Registered: ‎12-13-2010

Agree 100% with yandash.  This is exactly what I did.

 

The SelectIO IP configured as a CL transmitter is blatantly wrong.

bassman59
Historian
Historian
7,883 Views
Registered: ‎02-25-2008


@yandash wrote:

I also encountered the same issue and resolved it by driving 1100011 pattern through another OSERDES and have seen it work in hardware. I also opened a webcase on that in XILINX trying to understand why do they call their IP "Camera Link Transmitter" as this IP has nothing to do with Camera link apart from the fact it has 4 LVDS lanes with 1:7 serialization factor. Unfortunately, the XILINX support engineer seemed not familiar with Camera link so he did not understand what I was talking about...

Summary - generate the clock (and the camera link bits mixing as well) by yourself since XILINX do not really provide you Camera Link Transmitter IP.....


I haven't looked at this bit of Xilinx IP but it's not surprising that it isn't usable. 

Camera Link is more than just the serializers. There's the bit scrambling and the organizing pixel words into the bits required.

----------------------------Yes, I do this for a living.
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sunnow
Visitor
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Registered: ‎07-24-2008

Agree 100% with yandash.  This is exactly what I did.

 

The SelectIO IP configured as a CL transmitter is blatantly wrong.

 

I agree too.Clock forward in the IP wiszard for cameralink transmitter is a bug.  3:4 duty clock can be generate with OSERDES as well.  Actually Xilinx suggest this method in its XAPP1064 document on page 14.

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fsahebi2014
Explorer
Explorer
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Registered: ‎03-10-2015

hi jenslin,

 

-- declare the oserdes
clk_fwd : OSERDESE2
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "SDR",
DATA_WIDTH => 4,
TRISTATE_WIDTH => 1,
SERDES_MODE => "MASTER")
port map (
D1 => '1',
D2 => '0',
D3 => '1',
D4 => '0',
D5 => '1',
D6 => '0',
D7 => '1',
D8 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTOUT1 => open,
SHIFTOUT2 => open,
OCE => clock_enable,
CLK => clk_in,
CLKDIV => clk_div_in,
OQ => clk_fwd_out,
TQ => open,
OFB => open,
TBYTEIN => '0',
TBYTEOUT => open,
TFB => open,
TCE => '0',
RST => io_reset);

 

  Is the code from the IP. Did you change the setting of D1-D7 from 

D1 => '1',
D2 => '0',
D3 => '1',
D4 => '0',
D5 => '1',
D6 => '0',
D7 => '1',

 

 

to

 

D1 => '1',
D2 => '1',
D3 => '0',
D4 => '0',
D5 => '0',
D6 => '1',
D7 => '1',

 

To generate the 4:3 duty cycle clock? Appreciate your feedback.

 

Regards, Fred

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jenslin
Visitor
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Registered: ‎12-13-2010

yes that's what i did

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fsahebi2014
Explorer
Explorer
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Registered: ‎03-10-2015

Thanks alot. Did you do anything else? I have clk_in at 350MHZ, and clk_div_in at 50MHZ and they are phased aligned but

data out doesn't seems to be right. Please take a look at attached if you have time?

 

Best

selectio.PNG
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trenz-al
Scholar
Scholar
6,265 Views
Registered: ‎11-09-2013

Hi jenslin,

 

you said "yes that what  I did" to Fred, but did you look at his code he presented?

 

Fred is using OSERDES in DDR mode to shift out the cameralink clock, IMHO this is not working.

 

Sure if OSERDES SDR clock forwarding, then the clock forwwarding serdes would be in DDR mode, but not in the case of cameralink, where the cameralink clock is essentially a DATA lane that has 3:4 data bits ratio, those it toggles at SDR rate not DDR.

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fsahebi2014
Explorer
Explorer
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Registered: ‎03-10-2015

so what's the correct change then?

 

Regards, Fred

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reigngt09
Visitor
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Registered: ‎09-02-2015

I have had the same problem with the camera link aka select IO block in vivado. The bit mapping is totally off. Xilinx needs to change this or explain how to implement camera link with this block.

 

 

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