cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
matthew180
Explorer
Explorer
5,816 Views
Registered: ‎04-20-2010

Clock required?

Jump to solution

Is it possible to design a circuit that does not require a clock?  Will a FPGA and/or CPLD work without one?  Something like this:

 

q_out <=

  "0001" when sel_in = "00" else

  "0010" when sel_in = "01" else

  "0100" when sel_in = "10" else

  "1000";

 

If I had that in a 32 macrocell CLPD (or an FPGA, which would be overkill in this example), with the sel_in and q_out attached to I/O pins, would it work?  Or do these chips always require a clock of some sort to function?

 

Thanks,

Matthew

 

0 Kudos
1 Solution

Accepted Solutions
sonicwave
Explorer
Explorer
7,279 Views
Registered: ‎11-26-2008

You don't need a clock just for the sake of having a clock. If you are not using it in your design, it is not needed.

 

In any case, an "edge triggered latch" sounds like something you might as well call a flip-flop. You could try something like the following, which describes q_out as a flip-flop (which should thus retain its value):

 

 

signal d_reg std_logic_vector(3 downto 0);
 
d_reg <=
  "0001" when d_in = "00" else
  "0010" when d_in = "01" else
  "0100" when d_in = "10" else
  "1000";

process(trig_in)
begin
  if(falling_edge(trig_in)) then
    q_out <= d_reg;
  end if;
end process;

 

 

View solution in original post

6 Replies
gszakacs
Professor
Professor
5,815 Views
Registered: ‎08-14-2007

You don't need a clock to do purely combinatorial logic.  If you

need to have sequential logic you pretty much can't get away without

one, though.  CPLD's and FPGA's are not very good at making

asynchronous sequential logic.  Using a CPLD for purely combinatorial

logic is not really overkill unless you could do it more cheaply or in

a smaller footprint some other way.

 

Regards,

Gabor

-- Gabor
0 Kudos
matthew180
Explorer
Explorer
5,793 Views
Registered: ‎04-20-2010

Thanks for the info.  So what about combinatorial logic with an enable (is that considered a clock)?  What I need to do is reproduce a logic chip that is no longer in production, but I'd also make a change or two along the way.  Part of the chip is a falling edge triggered latch, so something like:

 

signal d_reg std_logic_vector(3 downto 0);

 

d_reg <=

  "0001" when d_in = "00" else

  "0010" when d_in = "01" else

  "0100" when d_in = "10" else

  "1000";

 

q_out <= d_reg when falling_edge(trig_in);

 

Assuming trig_in, d_in, and q_out are all tied to physical I/O pins, will something like this work?  The trig_in signal is picked up from a computer's we* signal, so it is not periodic by any means.

 

Also, I'm a little unsure about q_out since it is tied to output I/O pins.  Will q_out keep its value after the trigger, or do I need another register?  Something like this:

 

signal d_reg std_logic_vector(3 downto 0);

signal q_reg std_logic_vector(3 downto 0);

 

d_reg <=

  "0001" when d_in = "00" else

  "0010" when d_in = "01" else

  "0100" when d_in = "10" else

  "1000";

 

q_reg <= d_reg when falling_edge(trig_in);

q_out <= q_reg;

 

Is that necessary?

 

Matthew

 

0 Kudos
ahmedmohamed_45
Adventurer
Adventurer
5,788 Views
Registered: ‎07-14-2010

Hi

   working with input logic as a clock is completly bad i mad this mistake in my first project, by using the rising edge of an input signal it was a crazy system the best way is to use on input clock and sample trig_in as follow:

 

if rising_edge(clk) then

trig1<=trig2;

trig2<=trig3;

trig3<=trig_in;

 

if (trig1='1' and trig2='1' and trig3='0' and trig4='0') then

q_reg <= d_reg;

 

end if;

end if;

 

0 Kudos
drjohnsmith
Teacher
Teacher
5,753 Views
Registered: ‎07-09-2009

Hi

 

easy answer, is yes you can ,

 

Asyncronous or self clocking loigic is the fast future , if you belive some people.

 

but if your learning, dont,

   use syncronous logic, all the tools are geared towards syncronous logic.

 

not least, a clock input as an enable is called a latch,

   and it's not edge sensetive.

 

the rising_edge construct could be thought of as  'true or false'

   it enables the process,

     remeber the synths are trying to make silicon out of your text, so they are effectivly, and I know I will be shot for this,

      they are 'just' pattenr matching your text into the hardware.

           so if the synth does not understand you want a latch, or a register, good quesiton as to what your going to get.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
sonicwave
Explorer
Explorer
7,280 Views
Registered: ‎11-26-2008

You don't need a clock just for the sake of having a clock. If you are not using it in your design, it is not needed.

 

In any case, an "edge triggered latch" sounds like something you might as well call a flip-flop. You could try something like the following, which describes q_out as a flip-flop (which should thus retain its value):

 

 

signal d_reg std_logic_vector(3 downto 0);
 
d_reg <=
  "0001" when d_in = "00" else
  "0010" when d_in = "01" else
  "0100" when d_in = "10" else
  "1000";

process(trig_in)
begin
  if(falling_edge(trig_in)) then
    q_out <= d_reg;
  end if;
end process;

 

 

View solution in original post

matthew180
Explorer
Explorer
5,696 Views
Registered: ‎04-20-2010

Thanks sonicwave, that looks like exactly what I was looking for.  Now to see if it works as expected. ;-)

 

Matthew

 

0 Kudos