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Visitor
Visitor
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Registered: ‎09-08-2009

Clock skew balance issue

Dear :

    

     In my design, there is a IP which process data from different IO interface. Therefore I have to varify the function with clock domain switching.

 

As I know, all global clock element such as BUFG and BUFGUX come from BUFGCTRL primitive which has blance tree to FFs. But how the delay behavior between BUFGCTRLs ?

 

Is the dealy between BUFGCTRL is the same in FPGA silicon or in the same region (top / bottom) ?

 

If there is a regular delay between BUFGCTRLs, I will try to insert extra BUFG element to balance clock skew manually.

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