02-10-2010 08:04 PM
I want to bind any of the two components
(written using VHDL) to the top module and I don't want the other
component to be synthesized while synthesizing the top module.
But xilinx ISE synthesize all the components in the top module.
The components are complex than the simple gates considered in example below.
------ code example
-- gatesel is declared in package
If (gatesel=1) generate
a1: andg port map(....);
If (gatesel=2) generate
a1: org port map(....);
If (gatesel=3) generate
a1: xorg port map(....);
In this case, I expect any one of the component depends on gatesel value only to be synthesized. Can I control this in any way?
02-10-2010 11:05 PM
what is the problem? The time XST uses to (unnecessarily) synthesize the unused sources?
One solution is to synthesize the components individually, and provide only the presynthesized NGC Netlists in your toplevel project.
This way you only synthesize the components when they change. In your toplevel design they are seen as black boxes and filled up with the netlist information during implementation.
Have a nice synthesis
PS.: I'm not sure if partitioning is also a useful way to go. I think I read somewhere that partitions are recompiled only when they change in some way (source, synt. options).
02-11-2010 01:25 AM - edited 02-11-2010 02:03 AM
Thanks for your comments. Yes obviously the time matters for a complex designs which takes around an hour or so to synthesize the design. So using two such components in a project increases the execution time.