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arcpage
Visitor
Visitor
6,967 Views
Registered: ‎05-16-2011

Compiler Error

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Hello everyone,


I try to co simulate a design on a ML605, and this error appears :

 

FATAL_ERROR:Simulator:CompilerAssert.h:40:1.29 - Internal Compiler Error in file ../src/VhdlConcStmt.cpp at line 1574   Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
FATAL_ERROR:SimuUnsupported type : datacomplex for output: xout0
lator:CompilerAssert.h:40:1.29 - Internal Compiler Error in file ../src/VhdlConcStmt.cpp at line 1574   Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

 

I don't understand what I did wrong...

 

Can anyone help please ?

 

Thanks.

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arcpage
Visitor
Visitor
8,916 Views
Registered: ‎05-16-2011

Thanks.

I found the solution to the problem.

My design use a package in which user types are declared.

The hardware co simulation isn't able to parse correctly my design.

I had to make a wrapper in order to peel the user types in standard types in the port of the co-simulated instance.

Now it works.

View solution in original post

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8 Replies
drjohnsmith
Teacher
Teacher
6,961 Views
Registered: ‎07-09-2009

did you open a web case like it suggests ?

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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arcpage
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6,948 Views
Registered: ‎05-16-2011

Thanks for replying !

I'm not allowed to send the project.

I can't use the WebCase to solve the problem but I think it's internal to the compiler.

I checked the package where the type datacomplex is declared, and the syntax is correctly written.

 

 

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rcingham
Teacher
Teacher
6,945 Views
Registered: ‎09-09-2010
It might be correct accrding to the VHDL LRM, but is it a construct that XST suports?
BTW, which version of ISE, and what devices (ISE has version specific parsers)?

I can pretty much guarantee that if you can't post the code that causes it to barf, you won't get a useful answer...

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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arcpage
Visitor
Visitor
6,938 Views
Registered: ‎05-16-2011

I use ISE 13.1 with VHDL Source Analysis Standard VHDL-200X on a ML605. XST must support this package.

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rcingham
Teacher
Teacher
6,920 Views
Registered: ‎09-09-2010
Why must it?

------------------------------------------
"If it don't work in simulation, it won't work on the board."
drjohnsmith
Teacher
Teacher
6,919 Views
Registered: ‎07-09-2009

any synth supports a sub set of what is possible,

 

I've worked for many secure places, where we can't give out code,

   but

 

what I have always ben able to do if I have had a librarys problem,

   is reproduce it in a none related new project

 

doing this, a) says it is the libraries your calling up

    b) gives a smaller project that you can release to supportdesk.

 

and, I should say, it does not seem to me like a library problem,

   more like none optimum coding.

 

I have seen this sort of thing

    but when people are using none fpga IP, or graphic coding , like matlab / simulink.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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mcgett
Xilinx Employee
Xilinx Employee
6,913 Views
Registered: ‎01-03-2008

This isn't a "normal" ERROR message.  There is something in your code that the iSim simulator can't handle correctly and is generating software source code FATAL_ERROR.  If you can't provide the source files to official Xilinx support then there is little chance for anyone to find out what went wrong and provide a work around and an eventually software fix for this issue.

 

There is one small glimmer of hope in the second message "Unsupported type: datacomplex for output xout0".   Since only you have access to your source code and know what "xout0" is and what "datacomplex" is you are the only one that can attempt to debug this.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
arcpage
Visitor
Visitor
8,917 Views
Registered: ‎05-16-2011

Thanks.

I found the solution to the problem.

My design use a package in which user types are declared.

The hardware co simulation isn't able to parse correctly my design.

I had to make a wrapper in order to peel the user types in standard types in the port of the co-simulated instance.

Now it works.

View solution in original post

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