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Explorer
Explorer
10,087 Views
Registered: ‎11-24-2013

Constraint to generated counter clock

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Hi all,

 

I am using ISE 12 and I have in a hardware design a part that should work at a lower speed that the 200 MHz oscilator of my FPGA board. For doing that, I implemented a "clock divider" based on a counter.

 

Here's the VHDL code for such divider:

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity clk_div is
  Generic ( nBits  : integer := 7);
  Port    ( clk_HS : in STD_LOGIC;   -- High speed oscilator clock
            clk_LS  : out STD_LOGIC); -- Low speed generated clock
end clk_div;

architecture Behavioral of clk_div is

signal count : unsigned(nBits-1 downto 0);
signal MSB : std_logic; begin
cnt_proc: process(clk_HS) begin if(rising_edge(clk_HS)) then count <= count +1; end if; end process; BUFG_inst : BUFG port map ( O => clk_LS, I => count(nBits-1)
); end Behavioral;

 

And here's its RTL schematic:

 

Capture.JPG

 

I'm using this clock signal for driving another modules.

 

The problem comes when I go to the constraints editor, in Xilinx ISE, and I set the properties of the two clocks, the one of the oscilator an the divided clock I'm generating. I can set the period and its properties because it's detected as a clock...

 

Capture.JPG

 

... but I cannot select the outputs delay with respect to this generated clock. Only the oscilator, high speed clock is available in the list, as shown in the image below.

 

Untitled.png

 

So, I have two questions:

 

  1. Is it a good practise to drive the hardware with a clock generated into the FPGA by dividing the input clock?
  2. Why cannot I select the output offsets regarding the clock I'm generating? Is that normal?

Thanks in advance,

Ignacio.

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Instructor
Instructor
18,345 Views
Registered: ‎08-14-2007

Re: Constraint to generated counter clock

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The problem is that the tools don't follow the delay path from the input clock pin to the generated divided clock because it doesn't go through a "clock resource" like a DCM or PLL or MMCM.  OFFSET IN or OUT constraints only work on clocks that can be traced directly to a pin.  Your clock is considered an internally generated clock without a known phase relationship to a pin.  You could try to set an OFFSET OUT constraint on the original clock pin that drives the divider and see if the delay is properly traced through to the output pins clocked by the divided clock.

 

On the other hand it's generally considered bad practice to generate clocks this way, especially if you care about the phase of the divided clock relative to the pins.  Other choices would be using the CLKDIV output of a DCM, or making a clock enable using a fabric-based counter and run the slower logic with the original clock but a slow clock enable.  In some FPGA families you can also create a gated version of the input clock using a BUFG_CE.

-- Gabor
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2 Replies
Instructor
Instructor
18,346 Views
Registered: ‎08-14-2007

Re: Constraint to generated counter clock

Jump to solution

The problem is that the tools don't follow the delay path from the input clock pin to the generated divided clock because it doesn't go through a "clock resource" like a DCM or PLL or MMCM.  OFFSET IN or OUT constraints only work on clocks that can be traced directly to a pin.  Your clock is considered an internally generated clock without a known phase relationship to a pin.  You could try to set an OFFSET OUT constraint on the original clock pin that drives the divider and see if the delay is properly traced through to the output pins clocked by the divided clock.

 

On the other hand it's generally considered bad practice to generate clocks this way, especially if you care about the phase of the divided clock relative to the pins.  Other choices would be using the CLKDIV output of a DCM, or making a clock enable using a fabric-based counter and run the slower logic with the original clock but a slow clock enable.  In some FPGA families you can also create a gated version of the input clock using a BUFG_CE.

-- Gabor
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Explorer
Explorer
10,050 Views
Registered: ‎11-24-2013

Re: Constraint to generated counter clock

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Hi, Gabor,

 

thank you very much for your help!

 

Regards,

Ignacio

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