Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎06-29-2017

Cost comparison of masked SRAM write in ASIC and Zynq.

My knowledge of processes is mainly from old 0.18um technology camp, which may no longer apply in 28nm and lower. 


I am looking for information on the masking of data write in embedded SRAM for both FPGA and ASIC in today's 28nm processes. 

What is the approximate cost of byte or bit mask over normal 32-bit SRAM in ASIC? 


With regard to FPGA, would the usage of dual port RAM be still the same utilization as single port RAM, Since FPGA block RAM is dual port by default? Will adding a mask affect the resource utilization? 


My design is to minimize unnecessary memory accesses, i.e. reduce read change write operations if possible. 



0 Kudos
0 Replies