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jlqsczw_2007
Explorer
Explorer
11,448 Views
Registered: ‎06-28-2008

DCM-----locked or unlocked

Hello,everybody.

I met a question about the DCM of V5 240T.

 

My DCM input clock is given by DSP, the initial input clock is about 6 MHz when powered up. After about 3 seconds, the final input clock is given, it is about 100MHz.

Now I use chipscope to found that DCM did not locked for quite a while.

Then I redownload the bit file ,then DCM is locked-----Obviously I guess the reason is that the 100MHz input is stable so DCM locked quickly.

 

 

I simulated it and found the waveform was very weird.

 

The DCM is locked even if the clock disappeared.

The DCM is unlocked even if the clock is regiven again.

 

So what will happen when the " 6MHz first ,100MHz valid after 3 seconds "situation happened,

 

if the LOCKED signal is zero,  is the output clock of DCM  reliable and usable ???

 

////////////////////////////////////////////////////////////////////////////////

module t1_b;

 // Inputs

 reg clk_in;

 // Outputs

 wire clk_out;

 // Instantiate the Unit Under Test (UUT)

  b uut (   .clk_in(clk_in),   .clk_out(clk_out)  );

 

// uut is the DCM

 

 

 initial

 

 begin   

// Initialize Inputs  

 clk_in = 0;

  // Wait 100 ns for global reset to finish           

 repeat (20)begin    

 #10 clk_in = 1;   

  #10 clk_in = 0;    

 end    

#10 clk_in = 0;    

#1000 clk_in = 1;   

  repeat (20)begin    

 #10 clk_in = 1;    

 #10 clk_in = 0;    

 end    

#10 clk_in = 0;    

#1000 clk_in = 1;    

repeat (20)begin    

 #10 clk_in = 1;    

#10 clk_in = 0;    

end  

 // Add stimulus here

 

 end      

 

endmodule

 

dcm.jpg
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10 Replies
gszakacs
Professor
Professor
11,441 Views
Registered: ‎08-14-2007

Some things to note about the DCM:

 

The "LOCKED" signal will not change when there is no input clock.  It is a clocked signal.

 

There is a status output of the DCM, one bit of which (bit 2 IIRC) indicates loss of input

clock.  It is handy to AND this with LOCKED to make sure the DCM output is usable.

 

The DCM will not re-lock without being reset.  The standard reset circuit asserts the DCM

reset input for at least three input clock cycles after the input clock has becoms stable.

You must reset the DCM when the input frequency changes.

 

I have a standard DCM watch-dog circuit that detects loss of lock or input clock, and

counts up when either condition is true.  When the counter reaches a high value it

resets the DCM and holds it reset until the counter wraps back to zero.  The counter

is held reset when the DCM is locked and the input clock is running.  Thus as long

as the DCM locks before the counter gets to the threshold for resetting it, the counter

will stay reset and allow the DCM to continue to run.

 

-- Gabor

-- Gabor
barriet
Xilinx Employee
Xilinx Employee
11,435 Views
Registered: ‎08-13-2007

You should also familiarize yourself with the DCM specs in the V5 datasheet (ds202), e.g. frequency limits, how long it can take to lock (this likely explains one of your questions, e.g. Tlockmax), etc.

The v5 user guide can be a good intro, as well as XAPP462.

 

bt

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austin
Scholar
Scholar
11,421 Views
Registered: ‎02-27-2008

Don't do that:  reset the DCM once the input clock is stable.

 

Anything else, just will not work.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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jlqsczw_2007
Explorer
Explorer
11,405 Views
Registered: ‎06-28-2008

I also simulated PLL in ISim.

 

If the input clock changed or disappeared then appeared again,

 

the PLL will relock again.

 

So what are the major differences between DCM and PLL (I know one is digital another is analog )?? their advantages and disadvantages??

 

I used clk90 of DCM to meet the offset constraints in my project .

Although PLL also has clk90 and so on , I do NOT know if it can provide

precise and stable clock phase shift.

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gszakacs
Professor
Professor
11,398 Views
Registered: ‎08-14-2007

For a stable input clock, either DCM or PLL should provide a stable phase shift.  There is a fundamental

difference in the way the two achieve this.

 

The DCM uses a delay-locked loop.  This means that its outputs represent the input clock passing through

a tapped delay line.  Once locked, the output clock will have a constant delay from the input.  This means

that an input clock with jitter will pass the jitter through immediately.

 

The PLL uses a voltage controlled oscillator and a phase detector in a loop.  Once locked, the frequency of

the VCO matches the input frequency and the phase detector matches the output of the PLL to the input

by constantly adjusting the VCO frequency (a tiny bit).  This means that jitter in the input clock can take

some time to pass through to the output because it needs to get through the loop filter and into the

VCO adjustment.

 

If you use the clocking wizard and give it the properties of your input clock, it will estimate the jitter

of the derived clock for either DCM or PLL.

 

-- Gabor

-- Gabor
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jwilkinson7
Visitor
Visitor
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Registered: ‎11-20-2008

gabor, you said:

"There is a status output of the DCM, one bit of which (bit 2 IIRC) indicates loss of input clock.  It is handy to AND this with LOCKED to make sure the DCM output is usable."

 

Where is info about this status bit and how we can access it?   (for Virtex-5 in my case)

 

Thanks.

jeff

--
jeff wilkinson
jwilkinson@mail.com
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gszakacs
Professor
Professor
10,559 Views
Registered: ‎08-14-2007

Apparently the status output has been removed for the DCM_ADV in the Virtex 5.  Here's a screen shot from the Spartan 3 and Virtex 5 libraries guides.  Hopefully the LOCKED output of the DCM_ADV works more reliably than that of the Spartan 3.

-- Gabor
DCM_vs_DCM_ADV.PNG
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austin
Scholar
Scholar
10,552 Views
Registered: ‎02-27-2008

g,

 

The status is still there, on the data bus.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
jwilkinson7
Visitor
Visitor
10,526 Views
Registered: ‎11-20-2008

Ahh, now I see it, on D0(1), but it's only listed on the DCM_ADV.  

 

Thanks.

 

fwiw, here's the bit from the Virtex-5 Libraries Guide for HDL Designs (UG621) on that D0 bus.

 

The DO output bus provides DCM status when not using the dynamic reconfiguration feature, and a data output when using the dynamic reconfiguration. When showing DCM status, the following mapping applies:
• DO[0] - Phase-shift overflow
• DO[1] - CLKIN stopped
• DO[2] - CLKFX stopped
• DO[3] - CLKFB stopped
• DO[15:4] - Not assigned

 

This could be real useful to have it in the V5's.  The DCM's LOCKED output doesn't go to 0 when the clock goes away completely (at least it doesn't in sims).   As someone posted, it seems to be a registered signal.   Not sure who thought that was a good idea for that kind of status...   

I'm glad this alt status is still available.

 

thanks,

jeff

--
jeff wilkinson
jwilkinson@mail.com
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austin
Scholar
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Registered: ‎02-27-2008

Jeff,

 

The DCM being a synchronous digital machine, needs a clock to do anything at all.  So LOCK can't transition without a clock....

 

We decided that a clock lost signal, along with the fully synchronous lock, was a better solution that some kind of asynchronous kludge.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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