12-22-2014 06:49 AM
We are facing the problem in testing the DDR2 with Xilinx Memory controller.
We are not getiing init_calib_done. On Debug it was observed that VREF is jumping to 1.5v as soon as controller is trying to access the DDR2(Calibration Phase).
In normal condition(After Power Up) VREF is 0.9v. Please suggest on how to solve the issue.
FPGA : XC7A100T-1CSG324
12-22-2014 07:05 AM
Chek if vrefs pins are by mistake used in your XDC, also please start with pdf attached to below AR and see if you have followed all the design guideliness
12-22-2014 10:18 PM
Thank you for the reply.
We have cross verified the xdc and found no vref pins in xdc.
If required we will send you the project and schematic.
12-23-2014 11:04 AM