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anilsutej
Participant
Participant
6,136 Views
Registered: ‎01-07-2012

DDR2 interface with Artix-7

Hello,

 

We are facing the problem in testing the DDR2 with Xilinx Memory controller. 

 

We are not getiing init_calib_done. On Debug it was observed that VREF is jumping to 1.5v as soon as controller is trying to access the DDR2(Calibration Phase). 

 

In normal condition(After Power Up) VREF is 0.9v. Please suggest on how to solve the issue.

 

FPGA : XC7A100T-1CSG324

DDR2: MT47H64M16NF-25EL

 

 

Regards

Anil Sutej 

sch_ddr2_bank.png
SCH_DDR2.png
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3 Replies
vsrunga
Xilinx Employee
Xilinx Employee
6,132 Views
Registered: ‎07-11-2011

Hi,

 

Chek if vrefs pins are by mistake used in your XDC,  also please start with pdf attached to below AR and see if you have followed all the design guideliness

 

http://www.xilinx.com/support/answers/43879.html

 

 

Regards,

Vanitha

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anilsutej
Participant
Participant
6,107 Views
Registered: ‎01-07-2012

Hello Vanitha,

 

Thank you for the reply.

 

We have cross verified the xdc and found no vref pins in xdc. 

 

If required we will send you the project and schematic.

 

 

Regards

Anil Sutej 

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mcgett
Xilinx Employee
Xilinx Employee
6,091 Views
Registered: ‎01-03-2008

M12 should be connected to the DDR_VREF net on the board. This is not the reason for the voltage to go o 1.5V, but the system will a higher amout of errors with both VREF pins correctly connected.
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