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3,359 Views
Registered: ‎12-13-2011

DDR2 interfacing with Virtex-4

Hello,

I am trying to understand DDR2 interface with V-4. For that , I have coded the initlization sequence and then issued a read command to check if the initialization sequence was correctly interpreted by DDR2 or not. All I am expecting is a valid DqS signal which i am trying to capture by repetitive reads and shifting the FPGA clock using DCM variable phase shift. However the DQS is always zero - I am unable to capture the DQS signal on chipscope because of the clock limitations, so the only way is to debug using LEDs. Can anyone suggest if i am doing it the right way or any suggestions to crack the issue ?

 

 

Sachin

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Explorer
Explorer
3,342 Views
Registered: ‎08-12-2011

Re: DDR2 interfacing with Virtex-4

1. Try simulation first, including use of an RTL model of the external DRAM - they're a free download from most DRAM manufacturers.
2. Use on oscilloscope - is DQS toggling ?
3. Have you correctly tristated DQS before the read data is due ?
Remember DQS is a bidirectional signal.
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Highlighted
3,319 Views
Registered: ‎12-13-2011

Re: DDR2 interfacing with Virtex-4


I found the issue - it was wrong differential clock inputs to DDR. I can see the toggled DqS signals now. Thanks for your help escharbor.

 

Also Can I be sure of the initialization sequence being correct if I m getting DqS ? or is there a better way to check it than receiving DqS signals ?

 

 

Sachin

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Teacher
Teacher
3,317 Views
Registered: ‎09-09-2010

Re: DDR2 interfacing with Virtex-4

In simulation, you can look inside the DDR2 model to see if it has completed initialization properly.

The Micron DDR2 datasheet does not show any way of reading the initialization state. If you send the right sequence, and the memory then passes whatever BIST sequence that you choose to perform, it's good.

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"If it don't work in simulation, it won't work on the board."
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