02-05-2012 05:06 AM
I am trying to understand DDR2 interface with V-4. For that , I have coded the initlization sequence and then issued a read command to check if the initialization sequence was correctly interpreted by DDR2 or not. All I am expecting is a valid DqS signal which i am trying to capture by repetitive reads and shifting the FPGA clock using DCM variable phase shift. However the DQS is always zero - I am unable to capture the DQS signal on chipscope because of the clock limitations, so the only way is to debug using LEDs. Can anyone suggest if i am doing it the right way or any suggestions to crack the issue ?
02-05-2012 07:00 PM
02-09-2012 12:52 AM
I found the issue - it was wrong differential clock inputs to DDR. I can see the toggled DqS signals now. Thanks for your help escharbor.
Also Can I be sure of the initialization sequence being correct if I m getting DqS ? or is there a better way to check it than receiving DqS signals ?
02-09-2012 01:16 AM