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Anonymous
Not applicable
4,575 Views

DDR2 simulate problem

i have generated a ddr2 ip with MIG 3.3.but i can not  simulate it with the following error(modelsim SE 6.5e):

--------------------------------------------------------------------------------------

# ** Error: ../sim/sim_tb_top.vhd(578): (vcom-1136) Unknown identifier "j".
# ** Error: ../sim/sim_tb_top.vhd(578): Bad expression in left operand of infix expression "+".
# ** Error: ../sim/sim_tb_top.vhd(578): Actual (indexed name) for formal "bcs" is not a static signal name.
# ** Error: ../sim/sim_tb_top.vhd(662): (vcom-1136) Unknown identifier "j".
# ** Error: ../sim/sim_tb_top.vhd(662): Bad expression in left operand of infix expression "+".
# ** Error: ../sim/sim_tb_top.vhd(662): Actual (indexed name) for formal "bcs" is not a static signal name.
# ** Error: ../sim/sim_tb_top.vhd(716): (vcom-1136) Unknown identifier "j".
# ** Error: ../sim/sim_tb_top.vhd(716): Bad expression in left operand of infix expression "+".
# ** Error: ../sim/sim_tb_top.vhd(716): Actual (indexed name) for formal "bcs" is not a static signal name.
# ** Error: ../sim/sim_tb_top.vhd(767): (vcom-1136) Unknown identifier "j".
# ** Error: ../sim/sim_tb_top.vhd(767): Bad expression in left operand of infix expression "+".
# ** Error: ../sim/sim_tb_top.vhd(767): Actual (indexed name) for formal "bcs" is not a static signal name.
# ** Error: ../sim/sim_tb_top.vhd(814): VHDL Compiler exiting
# ** Error: E:/modeltech_6.5e/win32/vcom failed.

# Executing ONERROR command at macro ./sim.do line 69
# Model Technology ModelSim SE vlog 6.5e Compiler 2010.02 Feb 26 2010
# -- Compiling module HYB18T512160BF
#
# Top level modules:
#     HYB18T512160BF
# vsim +notimingchecks -L unisim -t ps -novopt work.sim_tb_top glbl
# Loading std.standard
# ** Error: (vsim-3173) Entity 'D:\xxx\DDR2\user_design\sim\work.sim_tb_top' has no architecture.
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./sim.do PAUSED at line 74

-------------------------------------------------------------------

 

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Explorer
Explorer
4,571 Views
Registered: ‎09-20-2007

You have not declared the variable j . should it be?

 

for i in 0 .. generate

 for j in 0 ....generate

FPGA freak
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Anonymous
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4,560 Views

Hi

yes, j has not  been defined in anywhere.

this file is generated automatically by MIG,so i don't know how i can fix it.

thanks for your reply

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Historian
Historian
4,540 Views
Registered: ‎02-25-2008

 


@sridar wrote:

You have not declared the variable j . should it be?

 

for i in 0 .. generate

 for j in 0 ....generate


the index variable in a for generate statement does not have to be declared.

 

----------------------------Yes, I do this for a living.
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Historian
Historian
4,539 Views
Registered: ‎02-25-2008

 


@Anonymous wrote:

i have generated a ddr2 ip with MIG 3.3.but i can not  simulate it with the following error(modelsim SE 6.5e):

--------------------------------------------------------------------------------------

# ** Error: ../sim/sim_tb_top.vhd(578): (vcom-1136) Unknown identifier "j".
# ** Error: ../sim/sim_tb_top.vhd(578): Bad expression in left operand of infix expression "+".
# ** Error: ../sim/sim_tb_top.vhd(578): Actual (indexed name) for formal "bcs" is not a static signal name.
# ** Error: ../sim/sim_tb_top.vhd(662): (vcom-1136) Unknown identifier "j".

-------------------------------------------------------------------

 


 

The scope that contains the failing lines does not have j declared.

 

BTW: the disclaimer header at the top of your source, the one that says, "this disclaimer and copyright notice must be retained as part of this file at all times" ?? DELETE IT. It's YOUR code, not Xilinx'.

 

----------------------------Yes, I do this for a living.
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