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Explorer
Explorer
3,865 Views
Registered: ‎11-23-2013

DDR3 controller and SSTL15_T_DCI in the same bank

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Hello,

 

I use HP banks of Virtex7 to implement DDR3 controller.

My controller will operate at 1600Mbps, so the VRN and VRP in the master bank should tie a 80Ω resistor to achieve higher performance. The middle bank which implements the addr/cmd signals is the master in the DCI_CASCADE.

 

And also in the addr/cmd bank, I want using the rest pins to transmmit and receive single end signals with the IOSTANDARD of SSTL15_T_DCI. Does the 80Ω external resistor applicable to SSTL15_T_DCI?

 

Thanks!

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Xilinx Employee
Xilinx Employee
5,168 Views
Registered: ‎07-11-2011

Re: DDR3 controller and SSTL15_T_DCI in the same bank

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Hi,

 

I think you are referring termination of your uused I/O pins (DQ/DQS) in the middle banks.

If they are used as inputs DCI would be sufficient, if outputs /bidirectoon then termination would be similar to ODT at memory end, which is set by mode register values. 80Ohms is typical value for Split Termination, however we strongly recommend to go for IBIS simulations and then take the final call

 

Regards,

Vanitha

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Xilinx Employee
Xilinx Employee
3,863 Views
Registered: ‎07-11-2011

Re: DDR3 controller and SSTL15_T_DCI in the same bank

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Hi,

 

DCI is not applicable for address and control, its IOSTANDRD is SSTL.

80Ω external resistor is not applicable to SSTL15_T_DCI

For address and control please refer UG586 termination guideliness section, it says

 

"Address and control signals (A, BA, RAS_N, CAS_N, WE_N, CS_N, CKE, ODT) are

to be terminated with the onboard DIMM termination. If DIMM termination does not

exist or a component is being used, a 40 pull-up to VTT at the far end of the line

should be used (Figure 1-88). Except for the CK/CK_N which requires a differential

termination as shown inFigure 1-90)

 

 

Edit:- Also all IOstanadards are not compatibel with SSTL_T_DCI, please go through UG471 

Rules for Combining I/O Standards in the Same Bank and take action accordingly

 

Do IBIS simulations for proper external terminatioon values.

 

 

Hope this helps

 

Regards,

Vanitha

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Explorer
Explorer
3,850 Views
Registered: ‎11-23-2013

Re: DDR3 controller and SSTL15_T_DCI in the same bank

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Hi, vsrunga

 

Yes, the addr/cmd bank doesn't use SSTL15_T_DC, which is SSTL15.

 

In my design, the addr/cmd signals' IOSTANDARD are SSTL15, which is not DCI. And I set the IOSTANDARD of unused pins in the addr/cmd bank as SSTL15_T_DCI.

I just apply 80Ω VRN and VRP in addr/cmd bank, and use "set_property DCI_CASCADE {34 36} [get_iobanks 35]" to set the addr/cmd bank as master. I used DCI_CASCADE here, so the VRN and VRP pins in the dq/dqs banks could be used as regular pins.

 

In ug586, it says "Single ended 40Ω traces and termination are required for operation at 1,333 Mb/s and higher". According to that, I choose the 80Ω external resistor.

 

I think the 80Ω could be applied to dq and dqs( IOSTANDARD is SSTL15_T_DCI and DIFF_SSTL15_T_DCI), it should be applicable to the pins defined by myself. Does what I think sounds right?

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Xilinx Employee
Xilinx Employee
5,169 Views
Registered: ‎07-11-2011

Re: DDR3 controller and SSTL15_T_DCI in the same bank

Jump to solution

Hi,

 

I think you are referring termination of your uused I/O pins (DQ/DQS) in the middle banks.

If they are used as inputs DCI would be sufficient, if outputs /bidirectoon then termination would be similar to ODT at memory end, which is set by mode register values. 80Ohms is typical value for Split Termination, however we strongly recommend to go for IBIS simulations and then take the final call

 

Regards,

Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
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Explorer
Explorer
3,836 Views
Registered: ‎11-23-2013

Re: DDR3 controller and SSTL15_T_DCI in the same bank

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Thanks for your reminding!

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