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Visitor
Visitor
2,604 Views
Registered: ‎03-03-2014

Data Assertion of AXI Crossbar v2.1 with two Slave Ports

Hello,

 

I have some issues with the AXI Crossbar v2.1 Vivado 2013.3 in SAMD when using two Slave Ports S0 and S1. As long as only one Slave Port S0 is used everything works just fine, but as soon as the other Slave Port S1 is used I get strange behaviour for read access. For Example after a read sequence like S0->S1, for every subsequent Read the corresponding data is asserted after one additional clock cycle, causing a mismatch with the assertion of the valid signal, which is now asserted one clock cycle before the data.

 

Simulation didn't show this behaviour at all, I saw it only by using Chipscope, additionally it does not happen in SASD mode.

 

Kind Regards

Steffen

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Xilinx Employee
Xilinx Employee
2,600 Views
Registered: ‎08-02-2011

Hi Steffen,

Can you post your chipscope dump/plots?

www.xilinx.com
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